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Urgent Help - DM642 VP2CTL2 pin configuration

Friends,

 

We are interfacing the DM642 VP2 to an LCD, which requires "DATA ENABLE".

 

In some DM642 video port display configuration parameters, VP2CTL2 stays low and does not toggle.

 

What are the required conditions for this output to operate correctly?

 

Below is our display port configuration structure.

 

Thanks,

 

Avi Tal

 

 

VPORTDIS_Params DM642_vDisParamsChan = {
    VPORT_MODE_RAW_16BIT,/* dmode:3    */ 
    VPORT_FLDOP_PROGRESSIVE,/* fldOp:3       */

    VPORT_SCALING_DISABLE,     /* scale:1       */   
    VPORT_RESMPL_DISABLE,      /* resmpl:1      */     
    VPORTDIS_DEFVAL_ENABLE,    /* defValEn:1    */
    VPORTDIS_BPK_10BIT_NORMAL, /*bpk10Bit:1 */
   
    VPORTDIS_VCTL1_HSYNC,  /* vctl1Config:2 */
    VPORTDIS_VCTL2_VSYNC,  /* vctl2Config:2 */
    VPORTDIS_VCTL3_CBLNK,  /* vctl3Config:1 */
    VPORTDIS_EXC_DISABLE,  /*extCtl:3      */
              
    680,                   /*frmHSize */
    425,                   /*frmVSize */

    1,                    /* imgHOffsetFld1 */
    1,                     /* imgVOffsetFld1 */
    LINE_SZ_640,               /* imgHSizeFld1   */
    NUM_LINES_480,             /* imgVSizeFld1   */
   
    0,                     /* imgHOffsetFld2 */
    0,                     /* imgVOffsetFld2 */
    0,                     /* imgHSizeFld2   */
    0,                   /* imgVSizeFld2   */

    640,                   /* hBlnkStart      */                   
    678,                   /* hBlnkStop       */                   
   
    640,                   /* vBlnkXStartFld1 */                   
    520,         /* vBlnkYStartFld1 */                   
    640,                   /* vBlnkXStopFld1  */                   
    0,          /* vBlnkYStopFld1  */                   
   
    0,                   /* vBlnkXStartFld2 */                   
    0,         /* vBlnkYStartFld2 */                   
    0,                   /* vBlnkXStopFld2  */                   
    0,         /* vBlnkYStopFld2  */                   

   
    1,                     /* xStartFld1 */                        
    0,           /* yStartFld1 */                        
   
    0,                     /* xStartFld2 */                        
    0,         /* yStartFld2 */                        

    (620),                 /* hSyncStart (total-backporch-frontporch)*/                        
    (640),                 /* hSyncStop  */                          
                          
    (640),                 /* vSyncXStartFld1 */                     
    (418+0),                     /* vSyncYStartFld1 */                     
    (640),                 /* vSyncXStopFld1  */                     
    (422+0),                     /* vSyncYStopFld1  */                     
     
    0,                   /* vSyncXStartFld2 */                   
    0,                   /* vSyncYStartFld2 */                   
    0,                   /* vSyncXStopFld2  */                   
    0,           /* vSyncYStopFld2  */
   
    0x10,                   /* yClipLow        */                   
    0xf0,                   /* yClipHigh       */
 
    0x10,                   /* cClipLow        */                   
    0xf0,                   /* cClipHigh       */
 
    0x0,                    /* VPDIS_DefVal    */                   
    0x0,
    0x0,
 
 
    VPORTDIS_RGBX_DISABLE,  /* rawPk_3_4 disable raw 3/4 packing for RGB output*/
    1,                      /* incPix, for raw mode only */         
    (LINE_SZ_640>>3),       /* thrld     */

    3,                      /* numFrmBufs*/
    128,                    /* alignment */
    VPORT_FLDS_MERGED,      /* mergeFlds */
    NULL,                   /* segId     */           
    EDMA_OPT_PRI_HIGH,      /* edmaPri   */
    8                       /* irqId     */   
};


VPORT_PortParams DM642_vDisParamsPort = {
    FALSE,                      /*  enableDualChan;     */
    VPORT_POLARITY_ACTIVE_LOW, //mm VPORT_POLARITY_ACTIVE_LOW, /* vport control pin 1 polarity    */
    VPORT_POLARITY_ACTIVE_LOW, /* vport control pin 2 polarity    */
    VPORT_POLARITY_ACTIVE_LOW, /* vport control pin 3 polarity    */
    &DRV_Fxns,
    INV,
};