Is there a document that discusses the GPMC signals' rise time and output source impedance? This information is required for high-speed PCB designs incorporating the DM3730.
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Hi Tsvetolin,
Section 10.1.5.3 talks about the timing of the various signals required to execute a read, write, etc. What I'm looking for is more so at the hardware level. I need to know the rise time of the address and data line signals. I also need to know the output impedance of the drivers of these signals. This info is needed to maintain good signal integrity in the PCB design.
Narek
Hello Narek,
The rise and fall times for the GPMC data signals for the DM3725 are located in the datasheet (http://www.ti.com/lit/ds/symlink/dm3725.pdf) in section 6.4.1 starting on pg. 160. The timing may vary depending on the mode being used. This information is located on the following tables:
6-4 (NOR Flash Synchronous mode)
6-8 (NOR Flash Asynchronous mode)
6-12 (NAND Flash Asynchronous mode)
The output impedance for these signals can be located in the technical reference manual mentioned above. In the register summary pages, the description for the GPMC registers state that the Transmission Line (TL) characteristic impedance is 50 Ohms. I located this in the register summary pages starting on pg. 2547.
Regards,
John Gracia