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am335x boot failed with samsung DDR3 K4B2G1646Q

x10
Intellectual 765 points
Other Parts Discussed in Thread: AM3352

Hi, All

My am335x based board is working fine with MT's DDR3 and Samsung's K4B2G1646C. When DDR3 is replaced with K4B2G1646Q, the board with u-boot can boot in case of power-up, but boot failed in warm reset. If WEC7+Eboot is burnt in, the board boot OK in both cases. The sdram_init function is already with parameters of K4B2G1646. With trace, I found the boot failed just after lowlevel_init and before jump to _main. Please let me know hot to fix this issue if anybody encountered similiar case. Thanks a lot.

BR

Cheng Shi

www.emtronix.com

  • 0
    TI__Guru**** 393215 points

    Hi Cheng,

    WEC is a third-party product and is not supported by TI. You can try contacting the software provider directly (Adeneo Embedded) or ask on the WinCE forum: http://e2e.ti.com/support/embedded/wince/f/353

  • 0 in reply to Biser Gatchev-XID
    Intellectual 765 points
    Hi, Biser

    In case of WEC, boot is fine, and my problem is with u-boot + Linux-3.12.10, :-)

    BR
    Cheng Shi
  • 0 in reply to Biser Gatchev-XID
    Genius 3685 points

    Samsung DDR3 RAMs may need a short delay after set up and before use.

    Try to insert udelay(5000) after DDR3 RAM init function in the first stage boot loader (MLO).

  • 0 in reply to Wolfgang Muees1
    Intellectual 765 points
    Hi, Wolfgang Muees1

    Thanks for you advice which is right! :-D

    BR
    Cheng Shi
  • 0 in reply to x10
    Genius 5250 points
    Dear Cheng Shi

    Even am trying to interface the same DDR

    Could you please provide me the u-boot configurations that you have done for DDR3 K4B2G1646Q with am335x



    Kindly do the needful

    Thanks in advance
  • 0 in reply to Srini
    Intellectual 765 points
    Here it is

    void sdram_init(void)
    {
    __maybe_unused struct am335x_baseboard_id header;

    if (read_eeprom(&header) < 0)
    puts("Could not get board ID.\n");

    if (board_is_evm_sk(&header)) {
    /*
    * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
    * This is safe enough to do on older revs.
    */
    gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
    gpio_direction_output(GPIO_DDR_VTT_EN, 1);
    }

    /* Samsung K4B2G1646x is used in EM335x, so that its own parameters are applied */
    if(board_is_em335x(&header)) {
    config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_em335x_data,
    &ddr3_em335x_cmd_ctrl_data, &ddr3_em335x_emif_reg_data, 0);
    udelay(5000); /* this is the delay!!!*/
    }
    else if (board_is_evm_sk(&header))
    ......


    BR

    Cheng Shi
    Emtronix
  • 0 in reply to x10
    Genius 5250 points
    Many Many Thanks a lot Cheng Shi, It is very much helpful

    As I just wanted to compare my configurations w.r.t K4B2G1646Q-BYK000 part number, could you please share the macro values that you have used for K4B2G1646EBIH9 interfacing with am3352

    #define K4B2G1646EBIH9_IOCTRL_VALUE
    #define K4B2G1646EBIH9_EMIF_READ_LATENCY
    #define K4B2G1646EBIH9_EMIF_TIM1
    #define K4B2G1646EBIH9_EMIF_TIM2
    #define K4B2G1646EBIH9_EMIF_TIM3
    #define K4B2G1646EBIH9_EMIF_SDCFG
    #define K4B2G1646EBIH9_EMIF_SDREF
    #define K4B2G1646EBIH9_ZQ_CFG
    #define K4B2G1646EBIH9_RATIO
    #define K4B2G1646EBIH9_INVERT_CLKOUT
    #define K4B2G1646EBIH9_RD_DQS
    #define K4B2G1646EBIH9_WR_DQS
    #define K4B2G1646EBIH9_PHY_WR_DATA
    #define K4B2G1646EBIH9_PHY_FIFO_WE
    #define K4B2G1646EBIH9_IOCTRL_VALUE


    am using K4B2G1646Q-BYK000 part number I have did the following configurations for the same as below

    #define K4B2G1646Q_EMIF_READ_LATENCY 0x100007
    #define K4B2G1646Q_EMIF_TIM1 0x0AAAD4DB
    #define K4B2G1646Q_EMIF_TIM2 0x266B7FDA
    #define K4B2G1646Q_EMIF_TIM3 0x501F867F
    #define K4B2G1646Q_EMIF_SDCFG 0x61C052B2
    #define K4B2G1646Q_EMIF_SDREF 0xC30
    #define K4B2G1646Q_ZQ_CFG 0x50074BE4
    #define K4B2G1646Q_RATIO 0x80
    #define K4B2G1646Q_INVERT_CLKOUT 0x0
    #define K4B2G1646Q_RD_DQS 0x38
    #define K4B2G1646Q_WR_DQS 0x44
    #define K4B2G1646Q_PHY_WR_DATA 0x7D
    #define K4B2G1646Q_PHY_FIFO_WE 0x94
    #define K4B2G1646Q_IOCTRL_VALUE 0x18B

    Kindly do the needful

    Many Many Thanks a lot in advance
  • 0 in reply to Srini
    Genius 5250 points
    Dear Cheng Shi,

    Could you please share the below configuration values that you have used to interface with am3352

    #define K4B2G1646EBIH9_IOCTRL_VALUE
    #define K4B2G1646EBIH9_EMIF_READ_LATENCY
    #define K4B2G1646EBIH9_EMIF_TIM1
    #define K4B2G1646EBIH9_EMIF_TIM2
    #define K4B2G1646EBIH9_EMIF_TIM3
    #define K4B2G1646EBIH9_EMIF_SDCFG
    #define K4B2G1646EBIH9_EMIF_SDREF
    #define K4B2G1646EBIH9_ZQ_CFG
    #define K4B2G1646EBIH9_RATIO
    #define K4B2G1646EBIH9_INVERT_CLKOUT
    #define K4B2G1646EBIH9_RD_DQS
    #define K4B2G1646EBIH9_WR_DQS
    #define K4B2G1646EBIH9_PHY_WR_DATA
    #define K4B2G1646EBIH9_PHY_FIFO_WE
    #define K4B2G1646EBIH9_IOCTRL_VALUE



    Kindly do the needful
    Many Thanks in advance
  • 0 in reply to Srini
    Intellectual 765 points
    The following are the parameters used which is included in TI's bsp package.

    #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
    #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
    #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
    #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
    #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
    #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
    #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
    #define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
    #define K4B2G1646EBIH9_RATIO 0x80
    #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
    #define K4B2G1646EBIH9_RD_DQS 0x35
    #define K4B2G1646EBIH9_WR_DQS 0x3A
    #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
    #define K4B2G1646EBIH9_PHY_WR_DATA 0x76
    #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B

    BR

    Cheng Shi
    Emtronix
  • 0 in reply to x10
    Genius 5250 points

    Dear Cheng Shi,

    Thanks a lot for your quick responses, it is greatly helpful for me for further analysis,

    Actually am awaiting for my custom board where this chip is mounted , so that I can validate my code changes on that board,

    Finally since you ported this macros for your board,

    Could you please let me know is there any other configurations that needs to be done fro DDR apart from the below structures & macros for DDR???

    ie., ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data, &ddr3_beagleblack_emif_reg_data


    am using K4B2G1646Q-BYK000 part number I have did the following configurations for the same as below

    #define K4B2G1646Q_EMIF_READ_LATENCY 0x100007
    #define K4B2G1646Q_EMIF_TIM1 0x0AAAD4DB
    #define K4B2G1646Q_EMIF_TIM2 0x266B7FDA
    #define K4B2G1646Q_EMIF_TIM3 0x501F867F
    #define K4B2G1646Q_EMIF_SDCFG 0x61C052B2 
    #define K4B2G1646Q_EMIF_SDREF 0xC30
    #define K4B2G1646Q_ZQ_CFG 0x50074BE4
    #define K4B2G1646Q_RATIO 0x80
    #define K4B2G1646Q_INVERT_CLKOUT 0x0
    #define K4B2G1646Q_RD_DQS 0x38
    #define K4B2G1646Q_WR_DQS 0x44
    #define K4B2G1646Q_PHY_WR_DATA 0x7D
    #define K4B2G1646Q_PHY_FIFO_WE 0x94
    #define K4B2G1646Q_IOCTRL_VALUE 0x18B

    void sdram_init(void)
    {
    config_ddr(400, K4B2G1646Q_IOCTRL_VALUE,
    &ddr3_beagleblack_data,
    &ddr3_beagleblack_cmd_ctrl_data,
    &ddr3_beagleblack_emif_reg_data, 0);
    }

    Kindly do the needful,

    Many Thanks in advance