OMAP4430 Power Domains

Hello David,

See the connections between power pins and power domains.

Device Power Pins --> Domain

vdda_csi21                  -->   CSI21 I/Os
vdda_csi22                  -->   CSI22 I/Os

This both pins are used for supplying CSI phy module.

vdda_hdmi_vdac          -->   HDMI PHY + ADPLL or TV-out video DAC

- This pin supplies HDMA and VDAC modules

vdda_usba_otg_1p8v   -->    USB PHY common module + ADPLL
vdda_usba0_otg_3p3v -->    USB PHY core module

- Those pins supply USB PHY modules.

To optimize the power consumption you must disable the IP modules CSI, HDMI and USB.

The necessary registers for this actions are in PRCM module. For more information see in OMAP4430 TRM document chapter3 PRCM.

CSI modules belong to Imaging Subsystem (ISS). In other hand, ISS Modules belongs to:

Voltage domain --> VDD_CORE_L

                             Power Domain --> PD_CAM

                                                        Clock Domain --> CD_CAM

To disable CSI module you must apply following sequence:

1. Disable clock signals from CD_CAM to ISS module by the registers:

Write in CM_CAM_ISS_CLKCTRL[1:0] MODULEMODE - 0x0 Module is disable by software
Set CM_CAM_CLKSTCTRL[1:0] CLKTRCTRL - 0x3: HW_AUTO: Automatic transition is enabled.

Check bits as read 0x1 - Read 0x1: Corresponding clock is running or gating/ungating transition is ongoing:

CM_CAM_CLKSTCTRL[8] CLKACTIVITY_ISS_CLK
CM_CAM_CLKSTCTRL[9] CLKACTIVITY_CAM_PHY_CTRL_CLK

The PRCM module provides a single clock (MPU_M3_ISS_CLK) to ISS power management. This clock generates the clocks for the Cortex-M3 MPU, ISS, and the bridges to L3. VDD_CORE_L (vdd)

NOTE:
To enable and access the ISS module, first the Cortex-M3 module must be enabled.

Check CM_CLKSEL_MPU_M3_ISS_ROOT[0] CLKSEL bit for MPU_A3/ISS root clock selection

You can select between CORE_MPU_M3_CLK and PER_MPU_M3_CLK clock signals.

2. Disable Power domain - PD_CAM - This register controls the CAM power state

PM_CAM_PWRSTCTRL[1:0] POWERSTATE - 0x0: OFF state

3. Voltage domain control:

PRM_VOLTCTRL[1:0] AUTO_CTRL_VDD_CORE_L - 0x0: Voltage domain transitions are disabled.

To disable HDMI module you must apply following sequence:
HDMI module belongs to power domain PD_DSS and clock domain CD_DSS and Voltage domain VDD_CORE_L.
To disable HDMI's clock:

Controls the clock state transition of the DSS clock domain.

CM_DSS_CLKSTCTRL[1:0] CLKTRCTRL - 0x3: HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.

CM_DSS_DSS_CLKCTRL[1:0] MODULEMODE - 0x0: Module is disable by software.

Check - CM_DSS_CLKSTCTRL[11] CLKACTIVITY_HDMI_PHY_48M_FCLK - Read 0x1: Corresponding clock is running or gating/ungating transition is ongoing

3. Set PD_DSS in OFF state:

 PM_DSS_PWRSTCTRL[1:0] POWERSTATE - 0x0: OFF state

To disable USB_OTG you must apply following sequence:

 USB_OTG or HSUSBOTG belongs to power domain PD_L3_INIT, clock domain CD_L3_INIT and voltage domain VDD_CORE_L.

1. Disable clocks to HSUSBOTG -

CM_L3INIT_HSUSBOTG_CLKCTRL[1:0] MODULEMODE - 0x0: Module is disable by software.
CM_L3INIT_HSUSBOTG_CLKCTRL[8] OPTFCLKEN_XCLK - 0x0: Optional functional clock is disabled

2. Disable power domain:

PM_L3INIT_PWRSTCTRL[1:0] POWERSTATE - 0x0: OFF state - Power state control

Best regards,

Yanko

Thank you. Can you reply to the following:

USB OTG - can we disable OTG_1P8 and OTG_3P3 and still wake on USB insertion. We disable OTG_3P3 but leave OTG_1P8 powered at the moment.

Hello David,

These pins supply following modules:

vdda_usba_otg_1p8v -->   USB PHY common module + ADPLL
vdda_usba0_otg_3p3v --> USB PHY core module

Ensure that the USBPHY_PD bit is set to 1 before the 3.3-V power supply (vdda_usba0otg_3p3v) to USB PHY is shut down. If this bit remains at 0 after the 3.3-V power supply is shut down and the 1.8-V supply to USB is on, some leakage might be seen on the 3.3-V supply.

Power down entire USB phy (data, common module and UTMI). controls USB2PHYCORE.PD pin.

CONTROL_DEV_CONF[0] USBPHY_PD - 0x1 Power down the USB PHY

I suggest you to see Table 3-341. Wake-up Sources during Device Low Power Mode. 

Wake-up sources can be HSUSBOTG; FSUSB modules.

If you disable (power down) these both pins you shut down  USB PHY core module and USB PHY common module + ADPLL. Therefore it is impossible to wake up on USB insertion. These module must be powered and you only must apply the necessary controls in PRCM module.

Best regards,

Yanko