slow time for accessing timers

Yogev Vaknin

Other Parts Discussed in Thread: AM3359, OMAP3530

I'm using AM3359 under linux (beaglebone black).

I have the following code, running in kernel mode (under timer interrupt, interrupts are disabled):

	curr_guard_val = omap_dm_timer_read_counter(goard_timer_ptr);

	new_d_tick = US_TO_TICK(d_us) -  (curr_guard_val - last_cap_val);

	/* set main timer */
	omap_dm_timer_set_load(timer_ptr, 1, 0xFFFFFFFF - new_d_tick - US_TO_TICK(w_us) - 100);
	omap_dm_timer_set_match(timer_ptr,1, 0xFFFFFFFF - new_d_tick - 100);
	omap_dm_timer_write_counter(timer_ptr, 0xFFFFFFFF - new_d_tick);


	omap_dm_timer_set_pwm(timer_ptr, /*SCPWM*/ 0 , /*PT*/ 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE);

	omap_dm_timer_start(timer_ptr);
	new_d_us = TICK_TO_US(new_d_tick);
	offset += TICK_TO_US(last_cap_val) - offset;
	end_handling = omap_dm_timer_read_counter(goard_timer_ptr);

The time for this simple code is 6-8 microsecond(very consistent), it was measured using (end_handling - curr_guard_val) and convert to microsecond. The CPU is working in 1Ghz and the relevant timers work with 24Mhz clock.

why does it take so long?

when the system is under-load(networking) the time for this code goes up to 12 microseconds. why?

Is it some how related to the post silicon errata titled "Delay Required to Read Some GP, WD, and Sync Timer Registers After Wake-Up" ?

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

Which Errata No. are you referring to? I can see no such errata in the AM335X Errata Rev. F. Also please post the Linux version you are using.

0 Yogev Vaknin over 10 years ago in reply to Biser Gatchev-XID

Prodigy 70 points

Hi,

I'm referring to the following errata:

"OMAP3530/25/15/03 Applications Processor Silicon Revisions 3.1.2, 3.1, 3.0, 2.1, and 2.0"

http://www.ti.com/lit/er/sprz278f/sprz278f.pdf

The kernel code also referring to it (arch/arm/plat-omap/include/plat/dmtimer.h):

 68 /*
 69  * timer errata flags
 70  *
 71  * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
 72  * errata prevents us from using posted mode on these devices, unless the
 73  * timer counter register is never read. For more details please refer to
 74  * the OMAP3/4/5 errata documents.
 75  */

The linux kernel version is 3.8.13-bone47 , and the distribution is Debian 7 (wheezy).

Thanks

0 Biser Gatchev-XID over 10 years ago in reply to Yogev Vaknin

TI__Guru**** 393215 points

This Linux version is not supported by TI. You can turn for support to the community at: http://beagleboard.org/Community/Forums This forum supports only the TI distributed Linux EZSDK.

0 Yogev Vaknin over 10 years ago in reply to Biser Gatchev-XID

Prodigy 70 points

Hi, the relevant code is identical to EZSDK V7.
The function calls is simply reading/writing from timer registers(The errata commit was written by Jon Hunter which is TI worker).

Anyway, can you tell me if the problem described in the errata effect the timer operation latency, and if so, for how long?
Can you tell me the expected time for the operation(5 times setting timer register, 2 reading timer counters) ?

Thanks

0 Biser Gatchev-XID over 10 years ago in reply to Yogev Vaknin

TI__Guru**** 393215 points

The relevant sections from the AM335X TRM Rev. K are 20.1.3.8 through 20.1.3.11. Please check if posted access is used. The timer OCP clock is 100MHz.

0 Yogev Vaknin over 10 years ago in reply to Biser Gatchev-XID

Prodigy 70 points

Thanks a lot. As i see it, the latency should be around 1 micro-second for all the operations.
I'm measuring ~6 microseconds, do you have any idea why this is happening ? maybe some side effect of the stalled CPU cycles?

0 Biser Gatchev-XID over 10 years ago in reply to Yogev Vaknin

TI__Guru**** 393215 points

I have no idea. Are you sure the measurement method is working correctly?

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slow time for accessing timers