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[OMAP3530] Problems in configure SDMA with McBSP2

Other Parts Discussed in Thread: SYSCONFIG

Hi !

I'm using a Mistral EVM Board (OMAP 3530) with Code Composer Studio 4 (CCS4), but I have some problems in configure e use SDMA with  McBSP2.

I'm setting the SDMA module to be active when McBSP2_TX is asserted and start to transfer data.. I'm configuring SDMA as below:

 

 

    DMA4_OCP_SYSCONFIG = 0x00000002;                      // Reset

    while ( (DMA4_SYSSTATUS & 0x00000001) == 0);       // Waits Finish Reset

    DMA4_CSR10 = 0x00001FFE;                                          // Reset Status Register

    DMA4_OCP_SYSCONFIG = 0x00001028;                     // Clock Free Running , DMA Ignores MSuspend Signal

    DMA4_CSDP10 = 0x00000001;                                       // Select Endiness For Source And Destination

    DMA4_CCR10 = 0x07081001;                                         // Select DMA Interrupt Request , Type Of Increment

    DMA4_CEN10 = 0x00000080;                                         // 128 Elements

    DMA4_CFN10 = 0x00000006;                                          // 6 Frame

    DMA4_CICR10 = 0x00000008;                                        // Enable End Of Frame Interrupt

    DMA4_CSSA10 = (unsigned int)TSP;                              // Source Start Address

    DMA4_CDSA10 = (unsigned int)0x49022008;               // Destination Start Address McBSP2_DXR

    DMA4_IRQENABLE_L0 = 0x00000400;                          // Enable Interrupt For Channel 10

    DMA4_CCR10 = DMA4_CCR10 | 0x00000080;             // Enable Logical Channel 

 

 

The McBSP2 is configure as below:

      McBSP2_SPCR2 = 0x00000200;       // Set Run Free Mode For TX And RX

 

      McBSP2_SPCR1 = 0x00000200;

      McBSP2_XCR2 = 0x00000000;          // Set 8 bits Transmitter With No Delay

      McBSP2_XCR1 = 0x00000040;          // Set 1 Word Per Frame 8 Bits Word

      McBSP2_PCR = 0x00000A0A;            // Set Frame Sync Mode With Polarity Low For TX Clock Polarity Negative , SCLKME = 0

      McBSP2_SRGR1 = 0x00000F01;      // Setting Up Frame Sync Width (16 Bits) And Clock Divider

      McBSP2_SRGR2 = 0x000012DE;      // Configure Clock Settings And Frame Width , CLKSM = 0 

      MCBSP2_XCCR = MCBSP2_XCCR & 0xFFFFFFF7;      // Set Interrupt For DMA 

      McBSP2_SPCR2 = McBSP2_SPCR2 | 0x00000040;      // Set Interrupt For DMA 

      McBSP2_SPCR2 = McBSP2_SPCR2 | 0x00000080;      // Enables Frame Sync Logic

      McBSP2_SPCR2 = McBSP2_SPCR2 | 0x00000001;      // Enables Transmitter

I'm configuring first the SDMA and then configure the McBSP2 (enable frame sync). 

 

All these configuration are made in DSP and I'm emulating it with XDS510 in CCS4.

Could anyone see something missing or some mistake I'm making?

I'm not configuring the RTSC and DSP/Bios files in CCS4, are they nedded ?

Could be something I'm not enabling, like INTC Module?

 

Tanks all. 

Best Regards