We are using DM365 in USB device mode, with multiple RX and TX transfers simultaneously on separate channels. After a few hours or more, the RX endpoint will eventually get stuck, but the TX endpoint is still running ok. When the RX endpoint is stuck, the channel register RCPPIDMASTATEW0: 80000000 which is described as Reserved in bits 31-8, so the 31 bit set is troubling. Can a TI engineer please let me know what that bit means and how to recover the RX channel?
Here is the full contents of the USB subsystem registers:
CTRLR: 00000000
STATR: 00000000
RNDISR: 00000005
AUTOREQ: 00000000
INTSRCR: 00000000
INTSETR: 00000000
INTCLRR: 00000000
INTMSKR: 01ff1e1f
INTMSKSETR: 01ff1e1f
INTMSKCLRR: 01ff1e1f
INTMASKEDR: 00000000
EOIR: 00000000
INTVECTR: 00000000
TCPPICR: 00000001
TCPPITDR: 80000000
TCPPIEOIR: 00000000
TCPPIMSKSR: 00000000
TCPPIRAWSR: 00000000
TCPPIIENSETR: 0000000f
TCPPIIENCLRR: 0000000f
RCPPICR: 00000001
RCPPIMSKSR: 00000000
RCPPRAWSR: 00000000
RCPPIENSETR: 0000000f
RCPPIENCLRR: 0000000f
RBUFCNT0: 00000003
RBUFCNT1: 00000004
RBUFCNT2: 00000003
RBUFCNT3: 00000000
CPPI channel 0 state block
TCPPIDMASTATEW0: 00000000
TCPPIDMASTATEW1: 83631800
Next=00000000 Buf=80110000 Off=618e Len=0000 SOP EOP EOQ Len=0000
TCPPIDMASTATEW2: 83631800
Next=00000000 Buf=80110000 Off=618e Len=0000 SOP EOP EOQ Len=0000
TCPPIDMASTATEW3: 8011618e
Next=00000000 Buf=0000 Off=0000 Len=0000 Len=0000
TCPPIDMASTATEW4: 00020000
TCPPIDMASTATEW5: 0000618e
TCPPICOMPPTR: 83631800
RCPPIDMASTATEW0: 00000000
RCPPIDMASTATEW1: 835c3880
Next=00000000 Buf=80360000 Off=0200 Len=0000 SOP EOP Own Len=0200
RCPPIDMASTATEW2: 00000000
RCPPIDMASTATEW3: 00000000
RCPPIDMASTATEW4: 00000000
RCPPIDMASTATEW5: 00000000
RCPPICOMPPTR: 4f7ca5eb
CPPI channel 1 state block
TCPPIDMASTATEW0: 00000000
TCPPIDMASTATEW1: 00000000
TCPPIDMASTATEW2: 00000000
TCPPIDMASTATEW3: 00000000
TCPPIDMASTATEW4: 00000000
TCPPIDMASTATEW5: 00000000
TCPPICOMPPTR: 65cb897d
RCPPIDMASTATEW0: 80000000
RCPPIDMASTATEW1: 835ae0a0
Next=00000000 Buf=81ad8400 Off=0200 Len=0000 SOP EOP Own Len=0200
RCPPIDMASTATEW2: 835ae080
Next=835ae0a0 Buf=81ad8200 Off=0200 Len=0000 SOP EOP EOQ Len=0200
Next=00000000 Buf=81ad8400 Off=0200 Len=0000 SOP EOP Own Len=0200
RCPPIDMASTATEW3: 835ae080
Next=835ae0a0 Buf=81ad8200 Off=0200 Len=0000 SOP EOP EOQ Len=0200
Next=00000000 Buf=81ad8400 Off=0200 Len=0000 SOP EOP Own Len=0200
RCPPIDMASTATEW4: 81ad8400
RCPPIDMASTATEW5: 00400000
RCPPICOMPPTR: 835ae080
CPPI channel 2 state block
TCPPIDMASTATEW0: 00000001
TCPPIDMASTATEW1: 835c2841
Next=00000000 Buf=801f0000 Off=1014 Len=0000 SOP EOP Own Len=1014
TCPPIDMASTATEW2: 835c2840
Next=00000000 Buf=801f0000 Off=1014 Len=0000 SOP EOP Own Len=1014
TCPPIDMASTATEW3: 801f0980
Next=00000000 Buf=0000 Off=0000 Len=0000 Len=0000
TCPPIDMASTATEW4: 00020694
TCPPIDMASTATEW5: 00001014
TCPPICOMPPTR: 835c2840
RCPPIDMASTATEW0: 00000000
RCPPIDMASTATEW1: 835ae8c0
Next=00000000 Buf=802a0000 Off=0040 Len=0000 SOP EOP Own Len=0040
RCPPIDMASTATEW2: 00000000
RCPPIDMASTATEW3: 00000000
RCPPIDMASTATEW4: 00000000
RCPPIDMASTATEW5: 00000000
RCPPICOMPPTR: ae5314a0
CPPI channel 3 state block
TCPPIDMASTATEW0: 00000000
TCPPIDMASTATEW1: 00000000
TCPPIDMASTATEW2: 00000000
TCPPIDMASTATEW3: 00000000
TCPPIDMASTATEW4: 00000000
TCPPIDMASTATEW5: 00000000
TCPPICOMPPTR: dbd0802b
RCPPIDMASTATEW0: 00000000
RCPPIDMASTATEW1: 00000000
RCPPIDMASTATEW2: 00000000
RCPPIDMASTATEW3: 00000000
RCPPIDMASTATEW4: 00000000
RCPPIDMASTATEW5: 00000000
RCPPICOMPPTR: 4a20746c
FADDR: 19
POWER: f0
INTRTX: 0000
INTRRX: 0000
INTRTXE: 001f
INTRRXE: 001e
INTRUSB: 00
INTRUSBE: f7
FRAME: 05e9
INDEX: 00
TESTMODE: 00
DEVCTL: 99
control and status register for endpoint 1
TXMAP: 0200
PERI_TXCSR: 2404
RXMAXP: 0200
PERI_RXCSR: 2000
RXCOUNT: 0000
HOST_TXTYPE: 00
HOST_TXINTERVAL: 00
HOST_RXTYPE: 00
HOST_RXINTERVAL: 00
control and status register for endpoint 2
TXMAP: 0200
PERI_TXCSR: 2000
RXMAXP: 0200
PERI_RXCSR: 2003
RXCOUNT: 0200
HOST_TXTYPE: 00
HOST_TXINTERVAL: 00
HOST_RXTYPE: 00
HOST_RXINTERVAL: 00
control and status register for endpoint 3
TXMAP: 0040
PERI_TXCSR: 3403
RXMAXP: 0040
PERI_RXCSR: 2000
RXCOUNT: 0000
HOST_TXTYPE: 00
HOST_TXINTERVAL: 00
HOST_RXTYPE: 00
HOST_RXINTERVAL: 00
control and status register for endpoint 4
TXMAP: 0000
PERI_TXCSR: 0000
RXMAXP: 0000
PERI_RXCSR: 0000
RXCOUNT: 0000
HOST_TXTYPE: 00
HOST_TXINTERVAL: 00
HOST_RXTYPE: 00
HOST_RXINTERVAL: 00
Also interesting that the author of the Linux driver for TI USB noted this same issue in the source code for the DMA driver module