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66AK2H12 EMIF Timing

UNA
Mastermind 7980 points

Other Parts Discussed in Thread: 66AK2H12

Hello,

I have a question about EMIF timing of 66AK2H12.
Please refer to the following descriptions on Datasheet.


According to the data sheet of td(EAITH-OEH) max values is defined as 23ns.
We were calculated as follows.

We are setting the SYSCLK1 is 1.2Ghz.
E = 1/(1.2Ghz/6) = 5ns
td(EAITH-OEH) = 4E + 3 = 4*5ns + 3 =23ns

However, We have measured its value was 28ns.

So, We think that specified value of the data sheet is minimum value.
Is My thinking correct?


Best regards,
H.U

  • 0
    TI__Mastermind 43660 points
    Hello H.U,

    I will check on this and let you know. Meanwhile could you please share the timing waveform that you captured in your board.

    Regards,
    Senthil
  • 0
    TI__Mastermind 42545 points
    Hi H.U,
    The design documentation definitely shows the 4E+3 as a maximum. The Wait signal is asynchronous and needs to be latched internally. Once it is latched the internal state machine will finish the access by de-asserting the OE and the CE. It appears that the SOC is taking an extra clock in your system. Can you provide a capture of the wait and OE signals measured as close to the SOC as possible? Remember that the rise and fall time of the wait signal may delay the point where it is latched internally. If the transition is slower, the time where the 4E+3 measurement begins may be delayed.

    Regards, Bill
  • 0 in reply to Bill Taboada
    Mastermind 7980 points

    Hi, Senthil, Bill

    Thank you for your reply.

    We have measured wait and OE signals as close to SOC as possible.
    We will send the waveform to you from TI local FAE.
    Because it is confidential information of our customer.

    Could you check it and give comment whether latch delay occur by wait signal?


    Best regards
    H.U

  • 0 in reply to UNA
    TI__Mastermind 42545 points
    Hi H.U,
    I've checked the waveform and I wanted to get an adjustment to the measurement. Clearly the signals were measured at the SOC since the wait signal looks clean and the OE signal has the flat section in the center. The flat section is caused by the reflection of the signal since it is being measured at the source. If you measured the signal at the destination, I would expect the rising edge to be clean but you would have to account for the delay associated with the length of the PCB trace. You placed your measurement point in the center of the flat section but I believe you should be measuring it at the beginning of the flat section. Your alternative is to measure the OE at the destination and calculate the delay through the PCB. If measured at the beginning of the flat section, is the number closer to 24nsec?
    Regards, Bill
  • 0 in reply to Bill Taboada
    Mastermind 7980 points

    Hi, Bill

    We were re-measured according to your comments, the number was 25.4ns.
    Why the big delay is observed? Is this affected by the internal latch timing of wait signal?
    We will send the new waveform to you from TI local FAE.

    Best Regards,
    H.U

  • 0 in reply to UNA
    TI__Mastermind 42545 points

    Hi H.U,

    Remember that the returning wait signals is not synchronous to the internal clock used by the EMIF interface. The wait signal must be latched twice to avoid a metastable condition. Once a valid wait has been clocked, the internal state machine must then act on that signal to end the memory access. Unfortunately this delay can't be reduced.

    Regards,

    Bill