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Question about Shared memory configuration with 6638K2K

ikhyun kim
Prodigy 70 points

1. Base condition

    - Each 8-CORE use differenct configuration file(or different project)

    - Shared memory(MSMC or external) use for CORE communication

      For example, "int x[100]" is shared with all cores.

 

2. Question

    - How "int x[100]" could be shared with all CORE.

 

    - One method is assign Dedicated address to that array and call  "x[100]" as pointer type.

    - The other method is using shared project.(Just like that exist in TI web site with CCSv4 condidion)

      I want to use shared project type first, but could not find sample code with CCSv5 environment.

 

      Could I get some sample code about shared project of globle variable.

3. I need a sample code in DOC "DSP_BIOS on Multi-Core sharedimage.pdf" which works in CCS V5 (not a CCSv4)

 

  • 0
    TI__Mastermind 18260 points

    The example that is illustrated in "DSP_BIOS on Multi-Core sharedimage.pdf" is an old DSP/BIOS example.  DSP/BIOS has been superceded by SYS/BIOS, which offers the same functionality as DSP/BIOS (and much more) but contains different APIs completely.  Do you need to stick with DSP/BIOS, or are you able to use SYS/BIOS (which I would strongly recommend, DSP/BOIS is many years out-of-date)?

    Do you need "IPC" functionality (which allows InterProcessor Communication and synchronization)?

    WIthout IPC, the basic method would be do define x[100] in each core's source file and place it in its own linker section with a #pragma DATA_SECTION directive, create the linker section and then hard-place it at some shared memory address of your choosing (by defining a linker MEMORY section that holds just the array).  SYS/BIOS provides tooling to do that without too much difficulty.  Then each core could access this array in the same place, although there isn't any protection against simultaneous writes to the array.  IPC provides various mechanisms for synchronization among cores, including GateMP which are MultiProcessor Gates that enable exclusive access to a critical section.

    IPC also provides SharedRegions in which a heap can be created and allocated from.  One core would allocate the array and then dynamically communicate the array's address to the other cores, using either IPC's Notify or MessageQ mechanism.

    Let me know which approach you would prefer and I can expand on the details.

    Regards,

    - Rob