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About DM8168 GPMC

Sean Shi
Prodigy 70 points

Hi, all.

The block diagram of my design is attached above.

My questions are:

1. Is this structure logical? Is the drive capability of GPMC bus enough in this backplane structure? If not, how to increase drive capability?

2. Considering the frequently inserting of IO cards, is there any solution to protect the GPMC bus?

3. In my design, ARM core controls nandflash, which connected to cs0. Is it possible that the DSP core controls the FPGA which connected to cs1, rather than via ARM core? In this design, real time communication between DSP and FPGAs are quite important.

  • 0
    TI__Guru**** 170625 points
    Hi Sean,

    1. To avoid signal degradation on rise/fall time, skew, voltage level, etc, please should check your system structure against the available IBIS model for the GPMC buffers using expected loading for your specific system

    2. Depending on the use cases, it may be necessary to protect the bus against ESD or current surge. Please ensure you are meeting the standard DM816x electrical spec for scenarios including card insertion/removal during either powered/non-powered conditions

    3. DSP cores can also be used to control the GPMC. If you intend to use both ARM and DSP cores to control the GPMC module, then special attention will be needed to ensure the two cores are not driving commands in conflict with each other

    Regards,
    Pavel