This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Questions On AM335x Power On

Two questions.

***

First, we are designing an AM335x/TPS65217C System-On-Module board, using Beaglebone Black as reference.

Since there are very few peripherals on board, we do not use an extra LDO for 3.3V power supply as BBB does.

Initially we connect all 3.3V VDDSHVx and peripherals to LDO4 (400mA output). Now we want to move some parts to LDO2 (200mA output), such as NAND, MMC, and EEPROM (for board id).

I examined the documents and found that LDO2 is ramping up slightly earlier than LDO4. That means, for example, NAND will power up before GPMC IO power is supplied.

If I use LDO2 to pull-up some interface signal, then these (mpu) signal lines will be pulled-up before the interface power ramping up (LDO4). Would that be an potential issue to fail the boot? or should I connect the power supply pin of NAND, MMC, and EEPROM to LDO2, but pull up the signal lines thru LDO4?

***

Second, on BBB, (MPU) VDDS can be connected to LDO1 or LDO3 thru jumper resistors. The default population is connecting to LDO1.

According to document, as long as the system has power supply, LDO1 will output automatically to VRTC and PMIC VIO, no matter if user have ever triggered the power-on-event by pressing power button or plugging in external power. If VDDS connects to LDO1, VDDS will be powered even if the system is off.

Is that a correct design? Or it doesn't matter? Connecting VDDS to LDO1 before system power up won't cause any problem during boot and the leakage current is negligible when system off?

***

Thanks

matianfu

  • Hi,

    For AM335X/TPS65217C connections please refer to the document: http://www.ti.com/lit/ug/slvu551i/slvu551i.pdf  On your questions:

    matianfu said:
    If I use LDO2 to pull-up some interface signal, then these (mpu) signal lines will be pulled-up before the interface power ramping up (LDO4). Would that be an potential issue to fail the boot? or should I connect the power supply pin of NAND, MMC, and EEPROM to LDO2, but pull up the signal lines thru LDO4?

    AM335X I/O pins are not fail-safe. Ideally VDDSHVx supply for the I/O pin connected to an external device should ramp up at the same time as the external device power supply.

    matianfu said:
    If VDDS connects to LDO1, VDDS will be powered even if the system is off. Is that a correct design? Or it doesn't matter? Connecting VDDS to LDO1 before system power up won't cause any problem during boot and the leakage current is negligible when system off?

    LDO1 is powered from VSYS, which is output from the TPS65217C. When the PMIC is turned off VSYS isn't present. There are switches inside the PMIC that turn it off. See "MODES OF OPERATION" and "WAKE-UP AND POWER UP SEQUENCING" in TPS65217C Datasheet.

  • Thank you very much, sir.