C64+ Atomic Interrupt

Geir

Hi,

I need to ensure that a HWI interrupt is always executed no matter what. It is a workaround used to ensure that the watchdog kicks in on the 6455. (Corrected in later HW by us).

So I am using TINTLO1 mapped to HWI 15. Which sets an GPIO pin.

But I have noticed on some occasions that the interrupt not always kicks in. The interrupt mask is set to all.

The requirement is simple, once the TINTLO1 kicks in, set the pin at any cost!

Any help would be appreciated.

over 11 years ago

0 Titusrathinaraj Stalin over 11 years ago

TI__Guru** 116100 points

Not a RTOS expert.

Have you changed the priority ?

http://processors.wiki.ti.com/index.php/SYS/BIOS_for_Stellaris_Devices#Configuring_a_Zero_Latency_Interrupt

0 Geir over 11 years ago in reply to Titusrathinaraj Stalin

Intellectual 335 points

Thanks,
Using the info in that wiki I defined a ISR outside the DSP/BIOS dispatcher that seems to do what we intend. I have not found any specifics on DSP/BIOS, but hoping that SYS/BIOS is not that far away, we'll go with that. There is no way to up the priority apart from finding an available int further up. Which was INT4.
Maybe one of your colleagues can verify that?

0 Titusrathinaraj Stalin over 11 years ago in reply to Geir

TI__Guru** 116100 points

Moved to RTOS forum to get better answers.

0 Ashish Kapania over 11 years ago

TI__Mastermind 21645 points

Hi Geir,

Are you building a SYS/BIOS (BIOS 6) or DSP/BIOS (BIOS 5) application ?

I am guessing in order to register an interrupt for intNum 15, you are creating a Hwi ? When do you see the interrupt mask being set to all ?

If you create an interrupt with disableMask set to all, then when this interrupt is serviced, it will disable all other interrupts (basically not allow nesting). The other interrupts will not be lost though. They will get executed once this interrupt is finished.

Best,
Ashish

0 Geir over 10 years ago in reply to Ashish Kapania

Intellectual 335 points

Hi,

sorry for late answer, had to travel.

Anyway, it's a BIOS 5 app. Once this interrupt is serviced it restarts the application by setting a GPIO pin (which flips the power system).
So what happens afterwords is a don't care.

It's mapped to HWI 4. DisableMass is set to all.

It seems to work, but how can I assure that this interrupt always triggers? No matter what?

This is a workaround for our earlier boards where the timer out pin was not connected to the power system, and hence the watchdog system do no work.

geir

0 Geir over 10 years ago in reply to Geir

Intellectual 335 points

Hi,
I'm stilling missing an answer to: If triggered, will this interrupt be served no matter what?
g

0 Ashish Kapania over 10 years ago in reply to Geir

TI__Mastermind 21645 points

Hi Geir,

If an interrupt is triggered, it will get serviced. It is possible that an interrupt is triggered while another interrupt is being serviced. In such a scenario, the new interrupt has to wait for the previous one to finish before it can be serviced.

Best,
Ashish

0 Geir over 10 years ago in reply to Ashish Kapania

Intellectual 335 points

Ok,
so an "Atomic interrupt" does not exist? In that case I'm happy.
geir

0 Ashish Kapania over 10 years ago in reply to Geir

TI__Mastermind 21645 points

Geir,

I am not sure I understand what you mean by "Atomic interrupt" ? Can you describe the term ?

Best,
Ashish

0 Geir over 10 years ago in reply to Geir

Intellectual 335 points

I understand an atomic interrupt as an interrupt type that is always served no matter what. It preempts any other.
geir

0 Ashish Kapania over 10 years ago in reply to Geir

TI__Mastermind 21645 points

Like I said before, the interrupt is guaranteed to get serviced. But, the interrupt will not pre-empt any other interrupt when it is triggered. I believe only NMI can pre-empt normal maskable interrupts on C64x.

Best,
Ashish

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C64+ Atomic Interrupt