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Jacinto 6 CPTS - unexpected TX event

Jakub Mielczarek
Intellectual 290 points

Hello,


I am facing an interesting issue with CPTS on Jacinto 6:

I am sending gPTP frames, CPTS works fine, TX events are reported by CPTS in the interrupt. After I reset CPTS (without power cycle), the first TX event I get from CPTS is: message id = 0, sequence id = 0, port = 1, timestamp (EVENT_LOW) = 0. The next TX event I get is valid and matches the gPTP frame I am actually sending. Even if I am not sending any gPTP frames after resetting CPTS I still get the unexpected TX event.


I am resetting CPTS in the following way:

1. Reset the CPTS module as - Clear the CPTS_EN bit in the CPTS_CONTROL register.
2. Write the CLKSEL_RFT value in the CM_GMAC_GMAC_CLKCTRL register in the PRCM with the
desired reference clock selection.
3. Set the CPTS_EN bit in the CPTS_CONTROL register.

Where is this unexpected TX event coming from? Any help would be appreciated.


Thank you,

Jakub

  • 0
    TI__Mastermind 29520 points

    Hello Jakub,

    I suggest you to see Tx function in drivers/net/ethernet/ti/cpsw.c:

    void cpsw_tx_handler(void *token, int len, int status)

    {

    struct sk_buff *skb = token;

    struct net_device *ndev = skb->dev;

    struct cpsw_priv *priv = netdev_priv(ndev);

    /* Check whether the queue is stopped due to stalled tx dma, if the

    * queue is stopped then start the queue as we have free desc for tx

    */

    if (unlikely(netif_queue_stopped(ndev)))

    netif_wake_queue(ndev);

    cpts_tx_timestamp(priv->cpts, skb);

    priv->stats.tx_packets++;

    priv->stats.tx_bytes += len;

    dev_kfree_skb_any(skb);

    }

    I saw in my GLSDK there is no such patch as - http://patchwork.ozlabs.org/patch/344886/


    Best regards,

    Yanko

  • 0 in reply to Yanko Todorov-XID
    Intellectual 290 points
    Hello Yanko,

    I am running the software on Cortex-M4 (one of the J6 CPUs). The OS is SYS/BIOS and the ethernet driver I have is not the Linux one.

    Best regards,
    Jakub
  • 0 in reply to Jakub Mielczarek
    TI__Mastermind 29520 points
    Hello Jakub,

    Are there any updates about your issues?

    The CPTS hardware will compare this field to the TS_LTYPE1 field or the TS_LTYPE2 field (depending on which enable bit was set) in the CPSW_TS_LTYPE register, which should also be programmed to 0x88F7.
    Once a transmitted or received packet is determined to be a valid time sync packet, the Ethernet Transmit Event or Ethernet Receive Event is loaded onto the Event FIFO.
    I suggest you to check this unexpected event as apply following sequence:
    1. Enable the TS_PEND interrupt by setting the CPTS_INT_ENABLE[0] TS_PEND_EN bit.
    2. Upon interrupt, read the CPTS_EVENT_LOW and CPTS_EVENT_HIGH registers values.
    3. Set bit of the CPTS_EVENT_POP[0] EVENT_POP register to pop the previously read value off of the event FIFO.

    Best regards,
    Yanko