• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 1579 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

GEL file mDDR settings for C6748 Custom board

Srinidhi Sreepad
Prodigy 190 points
Other Parts Discussed in Thread: TMS320C6748

Hello,

I am working on a custom board with a C6748 processor. It has mDDR memory of 512MB. The external input clock frequency is 15Mhz. The GEL file is modified accordingly, to match these settings. I could verify the PLL1 frequency of 150Mhz on the board using oscilloscope. But the debug session hangs after loading. I used the mDDR_DDR2_Memory_Controller_Register_Calc_Rev4.xls excel sheet to calculate the values of mDDR register. I found the following:

SDCR: 0x02034622

SDRCR: 0x00000492

SDTIMR1: 0x14923208

SDTIMR2: 0x380211C0

DRPHYC1R: 0x000000C4 

The PLL setup is:

Set_Core_300MHz() ---- device_PLL0(1,19,1,0,1,11,5);

Set_DDRPLL_150MHz() ---- device_PLL1(19,0,0,1,2);

Console:

C674X_0: Output: Target Connected to SR1.5
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Cleared.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: Memory Map Setup Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PSC Enable Complete.
C674X_0: Output: ---------------------------------------------
C674X_0: Output: PLL0 init done for Core:300MHz, EMIFA:25MHz
C674X_0: Output: mDDR initialization is in progress....
C674X_0: Output: PLL1 init done for DDR:150MHz
C674X_0: Output: Using mDDR settings
C674X_0: Output: mDDR init for 150 MHz is done
C674X_0: Output: ---------------------------------------------

 Are my calculations of the mDDR registers correct? How can I verify whether the register values are actually been set?

Thanks,

Sri

  • 0
    TI__Guru** 116100 points
    Hi Srinidhi,


    I am working on a custom board with a C6748 processor. It has mDDR memory of 512MB.


    Are you sure that you are using 512MiB mDDR ?

    As per the C6748 data sheet, you can interface mDDR/DDR2 with 256MiB.

    http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=tms320c6748&fileType=pdf
  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 190 points
    Hi Titus S.

    Thank you for your reply. The mDDR which we are using on the custom board is MT46H32M16LFBF-6 IT:C TR.
    http://www.micron.com/products/datasheets/a601d9c8-691f-4b45-964c-1d1940498553

    This mDDR is 512Mbits which is 64Mbytes (512Mbits/8). So I think it is compatible with the C6748.

    Thank you,
    Sri
  • 0 in reply to Srinidhi Sreepad
    TI__Guru** 116100 points
    Hi Sri,

    Thanks for the confirmation.


    I could verify the PLL1 frequency of 150Mhz on the board using oscilloscope. But the debug session hangs after loading.

    Able to access the memory (RAM 64MiB) through CCS memory browser after gel file loaded ?

    If you are not tried to access the memory access through memory browser then please avoid loading .out and try the memory access.