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C6655 help

TI Lady
Genius 4025 points

HI Keystone team,  I have a few questions for you please:

  1. With the latest product we are interfacing to 4 peripheral cards on a single McBSP bus. These  4 peripheral cards are connected to a backplane that connects to the processor card with the DSP on it. We were wondering if there is any advice with regards to layout and design when routing the McBSP to multiple devices. (We do not have much room with regard to the Codec presenting valid data and the DSPs required setup time on the DR.)
  2. We wanted to take a 10ns pulse to the timer input pin and from this produce a stretched 60ns pulse on the timer out pin. However table 7-78 of SPRS814A page 213 states that the minimum pulse duration is 12C, i.e. 12ns. Can you confirm that a 10ns pulse width is insufficient.

Thanks so much.

  • 0
    TI__Guru* 81335 points
    TI Lady,
    We are working with experts to answer this. Thank you for your patience.
  • 0 in reply to Raja
    Genius 4025 points

    Hi there,

    Just wanted to see if there was any update. This is hot.

    Thank you.

  • 0
    TI__Mastermind 43660 points

    Hello,

    With the latest product we are interfacing to 4 peripheral cards on a single McBSP bus. These  4 peripheral cards are connected to a backplane that connects to the processor card with the DSP on it. We were wondering if there is any advice with regards to layout and design when routing the McBSP to multiple devices. (We do not have much room with regard to the Codec presenting valid data and the DSPs required setup time on the DR.

    To my understanding, there is no specific routing guideline available for McBSP. However you need to ensure that your design must comply with McBSP timing requirement specified in section 7.22.2 McBSP Electrical Data/Timing in the device data manual.

    We wanted to take a 10ns pulse to the timer input pin and from this produce a stretched 60ns pulse on the timer out pin. However table 7-78 of SPRS814A page 213 states that the minimum pulse duration is 12C, i.e. 12ns. Can you confirm that a 10ns pulse width is insufficient.

    The minimum timer input requirment is 12C, where C is the CORECLK frequency. What is the CORECLK frequency (reference clock to the PLL) in your board ? Based on the CORECLK specification, the 10ns pulse to the timer input violates the requirement.

    Regards,
    Senthil

  • 0
    TI__Mastermind 42545 points

    1) Connecting to four peripheral cards will be difficult. It is important that the clock edges are clean at each of the components and that the data and frame sync signals meet the setup and hold times. If you are placing the components connected to the McBSP on daughtercards, clock buffering is recommended. Buffering the data is more difficult since each device must drive the data bits at different times. You should simulate your signals to be sure that they will arrive with the proper setup and hold.
    2) The input timer pulse is synchronized internally using the clock provided to the timer IP. That clock is used by the timer is the frequency provided to the DSP core divided by 6. If you are operating the DSP core at 1GHz, the timer pulse must be at least (1/(1GHz/6))*12 or 72ns. 10ns is not a sufficient pulse width for the timer input.
    Regards,
    Bill