power up sequence DM8148

Madhura,

Madhura Shetty said:

1. Is it possible to do external sequencing without that TPS659113

2.If it is possible then what is the sequence and  what is the 1-1 delay to  each supply

3. If i have some on board voltages like 3.3V,1.8V  can it  directly be used to DM8148 processor along with FPGA and other IC's

4.Is there any requirement to use separate regulators for DM8148  supplies

It is possible but hard to implement. You can do external sequencing without TPS659113 but you should be align with the DM814x sequencing described in the datasheet. This requires HW and SW changes (if you want to use DVFS). You can check this also in our PMU forum:

BR
Pavel

Madhura,

Madhura Shetty said:

3. If i have some on board voltages like 3.3V,1.8V  can it  directly be used to DM8148 processor along with FPGA and other IC's

See the DM814x TI EVM schematics.

BR
Pavel

Madhura,

Madhura Shetty said:

1. I referred DM8148 Mistral EVM for TPS659113 , but couldn't gather any information regarding power sequencing used in it.

The power sequence for DM814x is described in the DM814x technical documents (datasheet and TRM). The power sequence of TPS659113 is described in the technical documents of the TPS659113 chip:

Madhura Shetty said:

2. According datasheet all the 1.8V power can come up at once , then in EVM why they have generated different voltages for USB,HDMI and also for core voltage (CVDD_DSP,CVDD_ARM). Y cant they use same same rail for all core or 1.8V ? Is it because of the less current rating of the LDOs?
3. In EVM they have used 3 external regulators controlled by PMIC . one is DDR regulator, others are for LS_EVM_3.3V nad PCI_3V3. Can i use different regulators for theses rails while using TPS659113.
4. PMIC controls three other regulators in EVM , in which one uses 12 V as a supply and that particular regulator doesn’t support supply less than 10.8V and we don’t have 12V supply in our board.
5. Is it possible to use other regulators instead of three external regulators.
6.How to program EEPROM for sequencing

See if the DM814x TI EVM user guide will be in help:

MS_TI_DM814x_REVD_BB_HUG.pdf

Regards,
Pavel

The power-up sequence in DM814x datasheet and DM814x Silicon errata is with highest priority.

Madhura,

I think the DM814x TI EVM is the correct one (not TPS659113 document). You should double check this asking in the TPS659113 e2e forum:

Regards,
Pavel

Madhura,

Madhura Shetty said:

There are some confusion in power up sequence between DM8148 EVM and datasheet mentioned

According to datasheet 1.5V (DDR memory) should come first followed by 3.3V
But in EVM LDO3 and LDO 6 are used to generate TPS_GPIO_3V3 and TPS_VDD_CDC respectively.
TPS_GPIO_3V3 is not my concern as it is not connected to any of the processor power pins. But TPS_VDD_CDC is connected to VDDA_USB_3P3 in EVM which comes up PRIOR to DDR memory as per sequence mentioned in the TPS659113 user guide.

Doesn"t it contradicts the sequence mentioned in the datasheet of DM8148??

The DM814x datasheet is the correct source. This change come from the below silicon errata:

Advisory 3.0.82 Power Sequencing: DVDD_DDR[x] versus 3.3V DVDD* Supplies

Revision(s) Affected:  3.0, 2.1 [Data Manual Revision D and earlier]

Details: The Revision D and earlier Data Manuals permit the 3.3V DVDD* supplies to be ramped prior to the DVDD_DDR[x] supply. In this case, the internal pullup/pulldown (IPU/IPD) resistor for some pins may not be turned on until the DVDD_DDR[x] supply is ramped and stable. Once the DVDD_DDR[x] supply is ramped and stable, the IPUs and IPDs will function as expected.
Workaround: Ensure that the DVDD_DDR[x] supply is ramped and stable prior to ramping the 3.3-V DVDD* supplies.

For the actual "3.3-V DVDD*" power supply names, see the device-specific data manual.

Designs using the TPS659113 PMIC can take the following steps to provide the recommended power sequence.
– The PMIC provides GPIO0 and GPIO7 outputs that currently serve as enables for the discrete DDR and 3.3V power supplies, respectively. The PMIC activates the GPIO0 output 2 times slots (4ms) after the GPIO7 output, signaling the 3.3V power supplies to ramp 4ms before the DDR power supplies.
– The GPIO0 and GPIO7 signals can be swapped at the board level, instead connecting GPIO0 to the 3.3V power supply enable and GPIO7 to the DDR power supply enable. This will cause DVDD_DDR[x] to ramp 4ms before the 3.3V supplies and comply with the above recommended power sequence.

BR
Pavel

5807.Power Supply Sequence Alert - Release - DM38x-DM810x-DM812x-DM814x.pdf

Madhura,

Madhura Shetty said:

If i connect GPIO 7 to DDR enable and GPIO 0 3.3V supply problem will be solved as DDR will ramp 4ms prior to 3.3V supply.

No. The last version (ms_ti_dm814x_bbrevd_sch.pdf) of the DM814x TI EVM schematic is correct. The correct connection is PMIC/GPIO0 -> DDR3 1.5V and PMIC/GPIO7 -> 3.3V.

Madhura Shetty said:

But in EVM LDO3 and LDO6 are used to generate TPS_GPIO_3V3 and TPS_VDD_CDC respectively.
TPS_GPIO_3V3 is not my concern as it is not connected to any of the processor power pins. But TPS_VDD_CDC is connected to VDDA_USB_3P3 in EVM which comes up PRIOR to DDR memory as per sequence mentioned in the TPS659113 user guide.

From where you get this info? If from PMIC documents, please go and ask in the PMIC forum.

BR
Pavel