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Questions on TMS320c6748 LCDK technical reference and starterware

Other Parts Discussed in Thread: TMS320C6748, OMAPL138

Hi Experts,

I am working on the TMS320C6748 LCDK and i have a couple of questions:

1] Do we have a technical reference for the TMSXLCDK6748 that's something like this provided by the Spectrum Digital OMAPL138 EVM -

support.spectrumdigital.com/boards/evmomapl137/revd/files/EVMOMAPL137_TechRef_RevD.pdf

2] I could successfully get the McASP starterware example code up and running. I see that the default sample rate in the code is 48KHz. I would like to modify the codec sample rate to 8KHz. Would it be enough to change the "#define SAMPLING_RATE (48000u)" to 8000 in mcaspPlayBk.c or anyother change would be needed?


3] Also, are there any hardware accelerators (or assembly instructions) to implement a 400 tap filter in real time (for TMS320C6748)? [My application requires that the input analog signal be filtered with 400 taps in real time before being sent to the DAC] . Any pointers would be of immense help.

Thanks a lot

Smita

  • Also with reference to question [1] above, i have already had a look at all the reference mentioned in http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_%28LCDK%29 . So, any document on technical information specific to the TMDLCDK6748 would help.


    Thanks again!

  • 1] Do we have a technical reference for the TMSXLCDK6748 that's something like this provided by the Spectrum Digital OMAPL138 EVM -


    You can download the C6748 TRM in the following link.

    C6748 TRM -> http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

    C6748's all technical docs -> http://www.ti.com/product/TMS320C6748/technicaldocuments


    2] I could successfully get the McASP starterware example code up and running. I see that the default sample rate in the code is 48KHz. I would like to modify the codec sample rate to 8KHz. Would it be enough to change the "#define SAMPLING_RATE (48000u)" to 8000 in mcaspPlayBk.c or anyother change would be needed?


    Yup, thats sufficient.
  • Thank you! I passed two known sinusoidal tones at 2KHz - one  sampled at frequency 48KHz and the other at 8KHz and verified the outputs of CCS. I got what was expected and i could manipulate individual channel samples as well.  Works perfectly well.  Thanks! 

  • Hi,

    Thanks for your post.

    Just to address your question #3 and other two questions were already by Titus.

    I don't think, there are hardware accelerators or signal coprocessors in c6748 LCDK but you could implement your own software to design a 400 tap filter on DSP to process as applicable to your real time requirement.

    Thanks & regards,

    Sivaraj K

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  • Hi Sivaraj,

    Well yes, i could do it in software, but i was wondering whether implementing a 400 tap filter would be possible in real-time. I did some rough math and i think using a sampling frequency of 8KHz instead of 48KHz may be suitable; along with some heavy optimization and software pipelining. I'll use a logic analyzer to verify eventually.

    Also, may i know what's the maximum power consumption of the C6748 and how does it compare (in terms of power usage) with ultra low power C5000 series (I had a look at the documentation and i think standby power is <10mW. Could you please comment on power consumption while the CPU is up and running at top speed? i shall look into the TRM as well).

    Thanks a lot Sivaraj and Titus.

    Smita

  • Well, for closure, i've had a look and i think maximum power consumption at peak is around 400mW.