AM335x DDR3 SDRAM_CONFIG paramers explained

Brad Griffis said:

you should think of this as a setting for the external DDR3 device and not for the AM335x

Well it's a mix of the two of course. Bits 0-9,14-15,27-31 are EMIF config.

Thomas Kofoed-Hansen said:

I have read a lot of questions/answers about the REG_DDR_TERM, REG_DDR_DRIVE and REG_DYN_ODT paramerters in the SDRAM_CONFIG register in this forum, but non of them really give a full and understandable explanation of the possible values so that one with confident can choose the right setup.

Yeah, confronted with the RAM-config spreadsheet I also wished for a "how the *** should I know?" option for some of the settings. Even though point-to-point (single rank) fixed soldered-on RAM is the simplest case possible, when I researched the topic I still found different seemingly-authoritive sources giving different advice on drive strength and termination impedance.

I never reached a real conclusion, other than that RAM in this situation doesn't appear to be quite as fussy as I had feared. I think the real headache starts when you have multiple ranks, which the am335x doesn't support anyway.

In case it's of any use at all, here's what my own notes on that register say (although it's mostly the same info the TRM has but more concise):

bits  0- 2   #column bits - 8
bit   3      #rank bits = log2( #chip selects )
bits  4- 6   #bank bits
bits  7- 9   #row bits - 9
bits 10-13   (ram config)
bits 14-15   bus width:  0=32-bit  1=16-bit
     XXX note: on EMIFs with 64-bit bus (keystone),  0=64  1=32  2=16
bits 16-26   (ram config)
bits 27-28   #bank bits non-interleaved (must be <= #bank bits)
bits 29-31   ram type:  0=ddr1  1=mddr/lpddr1  2=ddr2  3=ddr3  4=lpddr2-s4  5=lpddr2-s2

ddr3 ram config:
bit  10      = 0
bits 11-13   cas latency - 3  (cycles, 2-7 for CL 5-11)
bits 16-17   cas write latency - 5  (cycles)
bits 18-19   ram output impedance:  0=34Ω  1=40Ω
bit  20      disable ram DLL
bits 21-22   ram termination for writes:  0=same as normal  1=60Ω  2=120Ω
bit  23      = 0
bits 24-26   ram termination:  0=off  1=60Ω  2=120Ω  3=40Ω  4=20Ω  5=30Ω

Micron also published some informative technotes, for example TN-41-13 may be of interest.

Thank you all for your input.

I have read the document from Micron but besides explaining certain things it just managed to generate more confusion and questions. Especially reading about ODT databus termination.

"The direct connect with ODT provides better signal quality and lower cost compared to series R. For ODT during writes, 40Ω, 60Ω, or 120Ω can be used with RTT_NOM versus 60Ω or 120Ω with RTT_wr. In most cases, 60Ω provides the best signalling."

As an example what are RTT_NOM and RTT_WR?

I recommend using IBIS models to determine the best combination.  Here's a link to a related wiki page on that topic:

Thomas Kofoed-Hansen said:

My understanding of ODT is that it's only used in multiple rank systems, where it's a question if the RAM is addressed for write in which case chooses one termination value (RTT_WR) and when not addressed chooses another termination value (RTT_NOM).

As the AM3356only supports single rank but still has the ODT setting programmable, what have I misunderstood?

No, that's not the case.  ODT is an impedance matching technique built into the processor and DRAM.  It's useful even for a single DDR3 memory attached to the bus.

Often ODT is confused with "Vtt".  The ODT applies only to the data bus.  It does NOT apply to the addr/ctrl signals.  For point-to-point systems like AM335x it is not necessary to terminate the addr/ctrl signals.  For devices using more than one DRAM component then it is usually advisable to apply Vtt termination using an external component like a TPS51200.

1258021 said:

How do I know what values to be programmed to SDRAM_CONFIG [19:18], [22:21] and [26:24]?
For example in above example for bits 18-19, 0 means 34 Ohms and 1 means 40 ohms. But, how should I arrive whether I need to use 34 ohms or 40 ohms value?

My impression from the micron TN is that they're suggesting

• 18-19 = 0 // RAM drives data with 34Ω (during reads)
• 21-22 = 1 // RAM terminates with 60Ω when receiving data (during writes)
• 24-26 = 0 // RAM applies no termination when not receiving data

From transmission line theory I'd normally expect drive and termination to both equal the impedance of the traces, but  1. this isn't available as option for termination  2. apparently reality in this situation doesn't quite conform the ideal theory; the TN says:

For point-to-point applications, a 34Ω driver with a 40Ω transmission line and a 60Ω termination provides the best, or near-best, solution. There is some mismatch, but with the DRAM and controller packages included, it provides the best solution.

Intuitively this sounds reasonable.

Note that the memory controller also needs to be configured to similar settings, by setting reg_phy_rd_local_odt in DDR_PHY_CTRL to apply termination during reads (for which that field needs to be 2 according to the TRM, which is slightly odd since it's 1 in other chips, but oh well) and configure the drive strength as explained in the Control Module chapter.