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Question about dm365 McBSP internal clock

Craig Smith
Intellectual 810 points

Hello,

I have a question about the internal clock going to the McBSP on the dm365 that is used by the sample generator (when you are not using the external signals as a clock reference).  According to the ARM user guide (sprufg5a.pdf), the McBSP's clock comes from PLLC1SYSCLK4. On our board, using the same default PLL settings from the EVM, this clock should be 121.5MHz.

That is, ( 24MHz (input clock) / 8 (prediv) ) * ( 2 * 81 (pll_mult) ) / 1 = 486MHz

PLLC1SYSCLK4 = 486MHz / 4 (pll4div) = 121.5MHz

So, according to Section 2.5.3 Data Clock Generation (McBSP user guide, spruf13a.pdf):

"The input clock to the sample rate generator, which can be either the internal clock source or a dedicated external clock source via the MCBSP_CLKX, MCBSP_CLKR, or MCBSP_CLKS pins. The McBSP internal clock is the CPU/6 clock...."

QUESTION 1: Is "CPU/6 clock" the PLLC1SYSCLK4 clock value divided by 6? i.e. 121.5/6 = 20.25MHz?

The McBSP user guide also says that this internal clock value is used to generate the bit clock by applying the CLKGDV in SRGR. If I set this value to 0 (no division), I observe 3.8MHz with a scope. I would have expected to see CPU/6 clock (20.25MHz).

QUESTION 2: If the internal input clock to the McBSP is CPU/6 clock, then where does 3.8MHz come from?

BTW, if I use 3.8MHz to compute the CLKGDV value for a desired rate (i.e. 48KHz for example, I set CLKGDV to 78) the results appear correct. I see a nice 48KHz clock on MCBSP_CLKX and the audio sounds correct. 

Can someone from TI please clarify these questions (or correct me if I'm wrong). Thanks.

Regards,

-Craig

 

  • 0
    TI__Intellectual 1375 points

    Craig,

    To answer question 1:  The "CPU/6 clock" is not correct.  It should be PLLC1SYSCLK4 = 486MHz / 4 (pll4div) = 121.5MHz.


    As for question 2: Can you double check the PLL registers to ensure you are getting a 121.5 mhz clock? If CLKGDV is set to 0, then you should get PLLC1SYSCLK4/2.  Also, check that the sample generator is not in reset.  Section 2.5.3.2 of the McBSP user guide (Example 1) provides some equations for helping out on this.

  • 0 in reply to Adam Barnett
    Intellectual 810 points

    Thanks Adam,

    It turns out that 3.8Mhz comes from the PLL1SYSCLK4/32. Where 32 = FPER+1. I verified that both clock signals out of the McBSP are correct 121.5MHz and 3.8MHz. 

    I was just confused by the "CPU/6" statement in the documentation (which still doesn't make sense so I'm glad you confirmed this is wrong).

    -Craig