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Tiva C Registers Question - TI-RTOS + Bootloader

Other Parts Discussed in Thread: SYSBIOS

Hello

I have a question to probe my understanding of the processor registers in the context of the bootloader.

In the normal case scenario when we develop program and run it MCU registers are set upon programing (1.?) where during execution we may need to manipulate individual bits such as global interrupts etc.

The pattern of zeros and ones must be provided (uploaded/programmed) for the correct program start and execution.

What happens when when we have the custom bootloader that resides at address 0x00 that was developed with tiva ware for example. The processor registers are programmed accordingly to the bootloader program.

The custom bootloader downloads the TI-RTOS program with the intention to run it upon successful completion. Will the TI-RTOS register configuration be set for the TI-RTOS allowing successful operation, or additional steps are required.


I use to work with Microchip bootloader in the past and remember issues around it.


I apologize if I'm not to clear.

Regards

Patrick

  • Hi Patrick,

    Which version of TIRTOS are you using?

    I think I need help to better understand what you are asking / trying to do.

    Are you trying to get an existing (working) TI-RTOS application to work with a custom boot loader that you have written yourself?

    Steve

  • Hello Steven

    Thanks for your email

    "Are you trying to get an existing (working) TI-RTOS application to work with a custom boot loader that you have written yourself?"


    Yes, you are correct and I have got this working with some issues that I got resolved.

    For example I have disabled global interrupts in the bootloader and the TI-RTOS was hanging after first few seconds before I have enabled the global interrupt at the TI_RTOS start.


    Following that issue I'm little bit concerned that if change the number of registers developing more complex code of the bootloader(downloading firmware through GPRS, decrypting, interrupts  etc) I will cause the bug in the TI-RTOS that will be very difficult to trace that will kick in occasionally. How can I assure this will never happen.

    I have managed to develop a large project based on TI-RTOS and I love it but it is still mystery for me what is happening under the hood of the TI-RTOS.

    Regards

    Patrick

  • Patrick,

    I want to point you to some documentation for XDC tools and SYS/BIOS (TI-RTOS kernel) that will provide you more information on the boot up sequence.

    • XDC Startup module
      • Details the XDC runtime bootstrap sequence and configuration
    • Boot module for the Cortex M4 on Tiva
      • Note that it will say "M3" in the title but this is for the M4
    • TI-RTOS kernel's BIOS module
      • Details the boot/start up sequence from SYS/BIOS' perspective
      • You can find this in your TI-RTOS installation.  For example, on my machine it's located here:
        • c:/ti/tirtos_tivac_2_10_01_38/products/bios_6_41_00_26/docs/cdoc/index.html
      • Just navigate to "ti/sysbios/BIOS" to get to the proper page.

    Steve