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RGMII IOStandard

Jon Jensen
Prodigy 90 points

We want to connect the C6472 to a processor using one of the RGMII ports. The problem is that the processor operates at 2.5 V LVCMOS and the C6472 operates at 1.5 V HSTL. Is there a way to configure the DSP for LVCMOS or somehow make the signals compatible?

  • 0
    Prodigy 90 points

    Also, I just noticed that the RGMII input timing requires a setup time of 1.2 ns and a hold time of 1.2 ns for a total data valid window of 2.4 ns. Can you confirm this is correct? I believe the RGMII spec requires an input data valid window of 2.0 ns at most.

  • 0
    Prodigy 90 points

    After doing some more research, I was able to find a voltage translation recommendation in the Hardware Design Guide for the C6472.

    At http://focus.ti.com/lit/an/spraaq4b/spraaq4b.pdf.

  • 0 in reply to Jon Jensen
    TI__Mastermind 42545 points

    The RGMII spec states that the minimum setup and hold times for the transmit data and transmit control is 1.2nsec at the transmitter assuming an internal delay.  Based on this the receive data and control will always be valid for a minimum of 2.4nsecs since these signals are always driven by a compliant transmitter.  If this is true then you may ask why the spec of the minimum setup and hold times for receive data and control are set to 1nsec.  The spec is set at 1nsec to compensate for any skew added due to the routing of the signals from one device to the other.  If the routing of the clock signal delays the edge relative to the data by 0.2nsec then your 1.2nsec setup and 1.2nsec hold at the transmitter becomes 1nsec setup and 1.4nsec hold at the receiver.  The data is still valid for 2.4nsec but it has shifted relative to the clock edge.  The C6472 Hardware Design Guidelines contain specific routing requirements for RGMII designed to minimize the skew between the clock and data signals which preserves the 1.2nsec setup and hold times from the transmitter to the receiver. 

  • 0 in reply to Bill Taboada
    Prodigy 90 points

    A little routing skew was what I was hoping to have. Since the receiver and transmitter have the exact same setup and hold times, then the trace delays for both clock and data have to be exactly the same and that is just not possible. That is why the spec requires the receiver to accept less strict setup and hold times. It still appears to me that the datasheet is violating the RGMII spec. Don't you agree?

    I mean we can match the lengths as best as possible, but the minimum input data valid window in the spec is 2.0ns and the C6472 minumim input data valid window is 2.4ns.