I am working on porting MIPI DSI LCD panel (Video mode) with Pandaboard ES Rev B3 , os is android 4.3 with kernel version 3.2.0
My panel spec is LCD size 320x480, HSA = 4 , HFP=10 ,HBP=3, VSA = 2 , VFP=43 ,VBP=2 , Frame rate = 60.03Hz
The current situation : When source code is executing "taal_power_on function" . It will send "0x11"(sleep out) to slave , but having DSI error.
Please tell me which reg setting or coding is not correct and tell me how to trouble shooting.
terminal console :
[ 4.669158] clock: disabling unused clocks to save power
[ 4.681823] omapfb omapfb: failed to apply dispc config
[ 4.692749] omapfb omapfb: failed to apply dispc config
[ 4.703674] omapfb omapfb: failed to apply dispc config
[ 4.710632] mmc1: queuing unknown CIS tuple 0x91 (3 bytes)
[ 4.722747] mmc1: new SDIO card at address 0001
[ 4.822448] omapdss DSI error: DSI CIO error, cio irqstatus 2
[ 4.828582] omapdss DSI error: rx fifo not empty after write, dumping data:
[ 4.835906] omapdss DSI error: rawval 0x000000
[ 4.835906] omapdss DSI error: unknown datatype 0x00
[ 4.845977] omapdss DSI error: dsi_vc_dcs_write(ch 0, cmd 0x11, len 1) failed
[ 4.845977] cmd sleep out implement
[ 4.845977] taal display0: error while enabling panel, issuing HW reset
[ 4.960174] omapfb omapfb: Failed to enable display 'lcd'
[ 4.960174] omapfb omapfb: failed to initialize default display
[ 4.972106] omapfb omapfb: failed to setup omapfb
[ 4.977050] omapfb: probe of omapfb failed with error -5
And my modified program as below:
static struct panel_config panel_configs[] = {
{
.name = "taal",
// .type = PANEL_TAAL,
.type = 0,
.timings = {
.x_res = 320,
.y_res = 480,
.pixel_clock = 10656,
.hsw=4,
.hfp=10,
.hbp=3,
.vsw=2,
.vfp=43,
.vbp=2,
},
.sleep = {
.sleep_in = 5,
.sleep_out = 5,
.hw_reset = 100,
.enable_te = 100, /* possible panel bug */
},
.reset_sequence = {
.high = 10,
.low = 10,
},
// printk("I called panel_config function");
},
};
static struct omap_dss_device sdp4430_lcd_device = {
.name = "lcd",
.driver_name = "taal",
.type = OMAP_DISPLAY_TYPE_DSI,
.data = &dsi1_panel,
.phy.dsi = {
.type=OMAP_DSS_DSI_TYPE_VIDEO_MODE,
.clk_lane = 1,
.clk_pol = 0,
.data1_lane = 2,
.data1_pol = 0,
.module = 0,
},
.clocks = {
.dispc = {
.channel = {
/* Logic Clock = 144M Hz*/ //144000000
.lck_div = 1,
/* Pixel Clock = 34.56 MHz */
.pck_div = 16,
.lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
// .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
.dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
.dsi = {
.regn = 25, /* Fint = 2.4 MHz */
.regm = 111, /* DDR Clock = 576 MHz One Lane = 288M Hz*/
.regm_dispc = 2, /* PLL1_CLK1 = 144 MHz */
.regm_dsi = 2, /* PLL1_CLK2 = 144 MHz */
.lp_clk_div = 9, /* LP Clock = 10.29 MHz */
// .offset_ddr_clk = 0,
.dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, //170.7M Hz
},
},
.channel = OMAP_DSS_CHANNEL_LCD,
};
And Debug Message as below :
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck 170666666
- DISPC-CORE-CLK -
lck 170666666 lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck 170496000 lck div 1
pck 10656000 pck div 16
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck 42666666 lck div 4
pck 42666666 pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint 1536000 regn 25
CLKIN4DDR 340992000 regm 111
DSS_FCK (DSS_FCLK) 170496000 regm_dispc 2 (off)
DSS_FCK (DSS_FCLK) 170496000 regm_dsi 2 (off)
- DSI1 -
dsi fclk source = DSS_FCK (DSS_FCLK)
DSI_FCLK 170666666
DDR_CLK 85248000
TxByteClkHS 21312000
LP_CLK 9472000
DISPC_REVISION 00000040
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000001
DISPC_IRQSTATUS 00000000
DISPC_IRQENABLE 0012d640
DISPC_CONTROL 00018308
DISPC_CONFIG 00020004
DISPC_CAPABLE 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_LINE_STATUS 00000000
DISPC_LINE_NUMBER 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD) 00200903
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD) 00202b01
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD) 00010010
DISPC_GLOBAL_ALPHA ffffffff
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD) 01df013f
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2) 00040001
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_BA0(OMAP_DSS_GFX) 00000000
DISPC_OVL_BA1(OMAP_DSS_GFX) 00000000
DISPC_OVL_POSITION(OMAP_DSS_GFX) 00000000
DISPC_OVL_SIZE(OMAP_DSS_GFX) 00000000
DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX) 000000a0
DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX) 04ff04f8
DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX) 00000500
DISPC_OVL_ROW_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX) 00000000
DISPC_OVL_TABLE_BA(OMAP_DSS_GFX) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_PRELOAD(OMAP_DSS_GFX) 00000100
DISPC_OVL_BA0(o) 00000000
DISPC_OVL_BA1(o) 00000000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 00000000
DISPC_OVL_ATTRIBUTES(o) 00008400
DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 00000000
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 00000100
DISPC_OVL_BA0(o) 00000000
DISPC_OVL_BA1(o) 00000000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 00000000
DISPC_OVL_ATTRIBUTES(o) 00008400
DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 00000000
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 00000100
DISPC_OVL_BA0(o) 00000000
DISPC_OVL_BA1(o) 00000000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 00000000
DISPC_OVL_ATTRIBUTES(o) 00008400
DISPC_OVL_FIFO_THRESHOLD(o) 07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 00000000
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_FIR_COEF_HV(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 00000100
DSI_REVISION 00000030
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 00000100
DSI_IRQENABLE 0015c000
DSI_CTRL 00faea98
DSI_COMPLEXIO_CFG1 60000021
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL 00344009
DSI_TIMING1 ffff7fff
DSI_TIMING2 ffff7fff
DSI_VM_TIMING1 02007001
DSI_VM_TIMING2 04022b02
DSI_VM_TIMING3 00fc01e0
DSI_CLK_TIMING 00000e0f
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00000000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00487296
DSI_TX_FIFO_VC_EMPTINESS 00000000
DSI_VM_TIMING5 0082df3b
DSI_VM_TIMING6 7a6731d1
DSI_VM_TIMING7 0012000f
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20800580
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000000
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20800d80
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000000
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20800d80
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20800d80
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 08110b0d
DSI_DSIPHY_CFG1 42030817
DSI_DSIPHY_CFG2 b8000006
DSI_DSIPHY_CFG5 60000000
DSI_PLL_CONTROL 00000000
DSI_PLL_STATUS 000001c9
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 0420de31
DSI_PLL_CONFIGURATION2 00656008
DSS_REVISION 00000040
DSS_SYSCONFIG 00000000
DSS_SYSSTATUS 00000001
DSS_CONTROL 00000001
THX
