When I use muticore DSP,I encounter the cache coherence and have known that how to solve the problems.But I am also confused about an question that does the cache coherence problem exsit in single core program?For examble as belows:
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/***********ISR function*********/
Arg=1
/********************************/
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Arg=0;
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/****************main************/
while(!Arg);
······
·····
/********************************/
The Arg is placed in MSMC and is not shared by other cores.In the main function,keep wainting until Arg becomes 1.The value of Arg changes when accepting an interrupt.Here is the problem:is it necessary to maintain cache coherence?Like this:
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/***********ISR function*********/
Arg=1
CACHE_wbL1d(&Arg, 16, CACHE_WAIT);
/********************************/
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A=0;
````
````
/****************main************/
while(!Arg)
{
CACHE_invL1d(&Arg, 16, CACHE_WAIT);
}
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·····
/********************************/
TMS320C6678
bios 6_33_05_46
ccs 5.2
Many thanks!
