On the EVMK2H, I use the PERF_CNT_1 and and PERF_CNT_2 registers to count the number of DDR3 reads and writes. It looks like they only count a fraction of the reads/writes, though. On the DSP, I configured the counters as follows:
hXmc->XMPAX[15].XMPAXL = 0x12101000 | 0xBF; // remap DDR3A controller into 32-bit address space
hXmc->XMPAX[15].XMPAXH = 0x21010000 | 0x0B;
hEmif->PERF_CNT_CFG = 0x00030002; // enable read & write counting
When executing this code:
for (int j = 0; j < 10000000; j ++)
dst[j] = dst[j+1];
I see that PERF_CNT_1 (configured as read counter) was incremented by 1252042 and PERF_CNT_2 (configured as write counter) was incremented by 5002263. So in this case, the read counter is incremented by 1 for every 64 bytes read, and the write counter once for every 16 bytes written.
However, when executing this code:
for (int j = 0; j < 10000000; j ++)
dst[j] = 0;
the write counter is incremented by 2502540, thus once for every 32 bytes written.
I would have assumed that each 8-byte read/write would count as one, but this is clearly not the case. Can somebody please explain me what these counters are really counting? And how can I count the total number of bytes transferred?
Thanks, John
