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Writing leveling minimum skew requirement

Tu Chau
Prodigy 20 points

In DDR3_design_sprabi1b, section 4.3.1.10, there is a minimum write leveling skew of 365 ps for DDR3-1333 in Table 18.  This translates into about 2.03 inches of trace difference between the command line and data line.  This is an awful long skew.  Can some one enlighten me on this?  If I only had one DDR3 memory chip, this requirement would mean I have to lengthen the data line by 2.03 in at least?  This is hard to understand !

  • 0
    TI__Mastermind 43660 points

    Hello Tu Chau,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    According to the design guide statement, "The maximum write-leveling skew is the largest difference between the two delays in the topology to a single SDRAM. Likewise, the minimum write-leveling skew is the smallest difference between the two delays in the topology to a single SDRAM". You are required to maintain the minimum skew; if not, the DDR3 interface may fail the write leveling process and data corruption may occur.

    You may find the below thread handy for your reference.

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/353277

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 20 points

    Thanks for such a quick response.  But my question is not completely answered.

    To follow what the routing guidelines tell me is one thing.  But to understand the reason is much more important.  What I want to know is WHY there is a minimum skew between trace lengths of the address/command/clock lines and the data lines.  When I looked at the memory chip timing diagram, one would expect to make the skew as small as possible.  But in this case, Keystone II requires the skew to be at least 2.07".  2 inches of skew on a small board translate into many meandering lines, especially there are more than 20 lines to deal with.  This requirement is counter intuitive.  Thanks. 

  • 0 in reply to Tu Chau
    TI__Mastermind 43660 points
    Hello Tu Chau,

    I believe the delay requirement is clearly explained in the section 4.3.1.10 of DDR3 design guide document. Since the DDR3 routing follows fly-by topology, it is mandatory to provide write levelling skew as recommended in the design guide.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    TI__Expert 4760 points

    Hi Cahau,

    The minimum and maximum skew requirement between the command delay and the data delay is to run the write leveling process successfully, if this limit is exceeded, the DDR3 interface may fail the write leveling process and data corruption may occur. This limit is sufficiently large so that well-controlled topologies will not likely exceed the limit.

    I can understand your criteria, the board is too small to achieve the minimum skew requirement, and these numbers are pretty generous so we don't believe it should cause any problems. , the values mentioned in the datasheet are proven topologies so, we stick to that values.

    Regards

    Antony                 

  • 0 in reply to Senthilkumar Srinivasan
    TI__Mastermind 42545 points
    Hi Tu Chau,
    The table that you are referencing has two sides, one with invert clock disabled and one with invert clock enabled.
    The definition of write leveling skew is the following.
    • write_levelingskew – defined as the value commanddelay - datadelay
    The write leveling skew must meet the minimum defined for the condition of the invert clock bit.
    If the invert clock is disabled, the numbers in the first two columns must be used. In this case the command delay must be 365ps greater then the data delay or the command bus must be 2.027" longer then the data bus.
    If the invert clock is enabled, the numbers in the second two columns must be used. In this case the command delay must be -385ps greater then the data delay. Since the minimum delay is negative, the command bus can actually be up to 2.138" shorter then the data bus.
    The invert clock feature was added specifically to support the customer using only a few memory components.
    Regards,
    Bill