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AM335x: UART timing for receiving

Kzk
Genius 5785 points
Other Parts Discussed in Thread: TL16C750

Hello,

I'd like to know the details about timing behavior for recieving data on AM335x UART module. How does the module detect a start bit for recieving data? My understanding is below. Is it correct? Please give me information.

BCLK has been driving and RX is high level. Then RX is changed state from high to low. The rising(or falling) edge of BCLK which is immediately after changing state of RX detects low level. This BCLK cycle is 1st for sampling. If the rising(or falling) edge of 8th BCLK is low, the module detects a start bit. (MDR.OSM_ SEL==0)

Regards,
Kazu

  • 0
    TI__Guru**** 393215 points

    Hi,

    The UART module is functionally compatible with the TL16C750 UART and is also functionally compatible to earlier designs, such as the TL16C550. You are correct that BCLK (which is 13x or 16x the actual baud rate) is used for syncing. Basically after a falling edge is detected as you say, the bit is also sampled at the 6-th (for 13x) or 8-th (for 16x) BCLCK pulse. If it's still low it's considered a start bit. After that each bit is sampled with a 13x or 16x BCLK offset.

  • 0 in reply to Biser Gatchev-XID
    Genius 5785 points

    Hello Biser,

    I'm very sorry, but I got part number wrong. It's AM180x as compatible with TL16C550. Our system is like noisy condition. Please let me check again to be sure. If the RX data from the 1st to the 15th BCLK are low, but the 16th BCLK is high, the module can recognize a start bit correctly, can't it? Does "offset" mean that the D0 bit which is next a start bit is sampled at falling edge of the 24th BCLK? (24=16+8 in 16x mode)

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Guru**** 393215 points

    The AM18X UART should be pretty much the same. There is a dedicated forum for it: http://e2e.ti.com/support/dsp/omap_applications_processors/f/42 You can ask there.