hi ,
am New in ADC working in Beagel Bone Black board & SDK7,
when reading all channels the data will come different manner
reading channel data through dev node ,
any body working this please reply me .
i/p voltage :1 v
o/p :ch0 - 3865 , ch1 - 47,ch2 - 49,ch3 -57,ch4 - 1907,ch5 - 2562 ,ch6 - 3352, ch7-3792.(default voltage )
Registers Configuration :
idle = ioread32(base_addr + ADCSTAT); //check ideal status or not
while(idle & (1<<5)) ;
clk_div = 0x40;
iowrite32(clk_div, base_addr + ADC_CLKDIV); //divide input ADC clock by 8 24M ,(32+1 )
cntl = ioread32(base_addr + CTRL);
cntl = cntl | (1 << 1); //TSC ADC tags
cntl = cntl | (1 << 2); //disable write protect
cntl = cntl | (1 << 5); //AFE_PENCTRL
cntl = cntl | (1 << 6); //AFE_PENCTRL
cntl = cntl | (1 << 7); //Transistor bias
iowrite32(cntl,base_addr + CTRL);
stpcnfg = stpcnfg |(1 << 6); // XPPSW_SWC
stpcnfg = stpcnfg |(1 << 8); //XNNSW_SWC
stpcnfg = stpcnfg |(1 << 10);
stpcnfg = stpcnfg |(3 << 19); // Channels changes
stpcnfg = stpcnfg |(4 << 2); // average 16 samples
iowrite32(stpcnfg,base_addr + STEPCONFIG1); //stepconfig reg 1
stepen = stepen |(1 << 1); //enable 1 stepconfig register
stepen = stepen |(1 << 2); //enabled 2 stepconfig register/
iowrite32(stepen,base_addr + STEPENABLE);
adcs = ioread32(base_addr + CTRL);
adcs= adcs |(1 << 0); //Enable TSC_ADC_SS/
iowrite32(adcs,base_addr + CTRL);
data = ioread32(base_addr + FIF0DATA); //FIFO0_data
val = copy_to_user(buf,&data,4);
printk("FIF0_DATA = %d\n",(data&0xFFF));
Thanks & Regards,
Naveen,