Hi,
I am testing the PCIE PHY loopback on a TCI6638K2K board.
Currently i am using sample example as given in pdk_keystone2_3_01_01_04 for pcie, k2k device.
I have proceeded as given below:
In pcie_sample.c file.
1. EVM board is configured in RC mode.
2. Serdes is configured as :-
-> CSL_PCIeSerdesInit(CSL_PCIE_SERDES_CFG_REGS, CSL_SERDES_REF_CLOCK_100M, CSL_SERDES_LINK_RATE_5G);
-> CSL_PCIeSerdesSetLoopback(CSL_PCIE_SERDES_CFG_REGS, i, CSL_SERDES_LOOPBACK_ENABLED);
-> CSL_PCIeSerdesLaneEnable(CSL_PCIE_SLV_CFG_REGS, 1);
-> CSL_PCIeSerdesSetLaneRate(CSL_PCIE_SLV_CFG_REGS, CSL_SERDES_PCIE_GEN_2);
-> CSL_PCIeSerdesGetStatus(CSL_PCIE_SERDES_CFG_REGS, 1);
My SerDes is configured successfully.
3. Then Configure application registers for Root Complex.
4. Enable link training -> Force pcie link state (If i do not do this, link do come up) -> pcieWaitLinkUp
5. Push a single message to the EP then verify that it is echoed back
But there is no message coming back.
Console:
======================================================================================
**********************************************
* PCIe Test Start *
* RC mode *
**********************************************
Version #: 0x02010001; string PCIE LLD Revision: 02.01.00.01:Feb 5 2015:16:50:41
Debug: Serdes Setup Successfully
Power domain is already enabled. You probably re-ran without device reset (which is OK)
PCIe Power Up.
PLL configured.
Successfully configured Inbound Translation!
Successfully configured Outbound Translation!
Starting link training...
Force PCIe Link state...
Debug0 Value #: 0x00826968
Link is up.
======================================================================================
I have following questions:-
Q1. Please suggest what is missing?
Q2. Is internal PHY loopback is working on this EVM board?
Q3. What else i need to do make it work?
Please help.
Regards,
Praveen