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PCIe PHY loopback on PCI6638K2K EVM

Other Parts Discussed in Thread: TCI6638K2K

Hi,

I am testing the PCIE PHY loopback on a TCI6638K2K board.
Currently i am using sample example as given in pdk_keystone2_3_01_01_04 for pcie, k2k device.
I have proceeded as given below:
 In pcie_sample.c file.
1. EVM board is configured in RC mode.
2. Serdes is configured as :-
 -> CSL_PCIeSerdesInit(CSL_PCIE_SERDES_CFG_REGS, CSL_SERDES_REF_CLOCK_100M, CSL_SERDES_LINK_RATE_5G);
 -> CSL_PCIeSerdesSetLoopback(CSL_PCIE_SERDES_CFG_REGS, i, CSL_SERDES_LOOPBACK_ENABLED);
 -> CSL_PCIeSerdesLaneEnable(CSL_PCIE_SLV_CFG_REGS, 1);
 -> CSL_PCIeSerdesSetLaneRate(CSL_PCIE_SLV_CFG_REGS, CSL_SERDES_PCIE_GEN_2);
 -> CSL_PCIeSerdesGetStatus(CSL_PCIE_SERDES_CFG_REGS, 1);
 
My SerDes is configured successfully.

3. Then Configure application registers for Root Complex.
4. Enable link training -> Force pcie link state (If i do not do this, link do come up) -> pcieWaitLinkUp
5. Push a single message to the EP then verify that it is echoed back

But there is no message coming back.

Console:

======================================================================================

**********************************************
*             PCIe Test Start                *
*                RC mode                     *
**********************************************

Version #: 0x02010001; string PCIE LLD Revision: 02.01.00.01:Feb  5 2015:16:50:41

Debug: Serdes Setup Successfully
Power domain is already enabled.  You probably re-ran without device reset (which is OK)
PCIe Power Up.
PLL configured.
Successfully configured Inbound Translation!
Successfully configured Outbound Translation!
Starting link training...
Force PCIe Link state...
Debug0 Value #: 0x00826968

Link is up.

======================================================================================

I have following questions:-

Q1. Please suggest what is missing?
Q2. Is internal PHY loopback is working on this EVM board?
Q3. What else i need to do make it work?

Please help.

Regards,
Praveen

  • Hello Praveen,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    Your query will be addressed soon.

    Regards,
    Senthil
  • Hi Praveen,

    I have tested PCIe PHY loopback on C6678 EVM board. the same initialization steps are enough for K2K EVM.

    Ans1 and Ans3: Please take a look at below e2e link.
    e2e.ti.com/.../1244423

    Ans2: Yes

    Thanks,
  • Hi Ganapathi,

    I have checked these links already..After going through lots of e2e discussion..I had proceed for the same.

    One more thing I also tried same PCIE PHY loopback on PCI6670, But there i am struck in given below code.

     /* Data sent to EP.
           RC waits for the loopback to be completed and
           receive data back from EP */

        do {
          unsigned int key;

          /* Disable Interrupts */
          key = _disable_interrupts();

          /*  Cleanup the prefetch buffer also. */
          CSL_XMC_invalidatePrefetchBuffer();    

          CACHE_invL1d ((void *)dstBuf.buf,  PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);
          CACHE_invL2  ((void *)dstBuf.buf,  PCIE_EXAMPLE_DSTBUF_BYTES, CACHE_FENCE_WAIT);

          /* Reenable Interrupts. */
          _restore_interrupts(key);

        } while(dstBuf.buf[PCIE_BUFSIZE_APP] != PCIE_EXAMPLE_BUF_FULL);

    My code struck in CACHE_invL1d function and in for CACHE_FENCE_WAIT ->_mfence();

    My dstBuff is also empty.

    Can you please suggest How to proceed further?

    Thanks,

    Praveen

  • I have successfully tested the PCIe PHY loopback on C6670 EVM board. Share your test code, i will try to resolve your issue.