Other Parts Discussed in Thread: 66AK2H12
hi, everyone
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my system configuration : 66AK2H12 and virtex7 FPGA(xc7v2000t) were connected via SRIO.
1. using example project : SRIO_LoopbackK2HC66BiosTestProject.
loopback mode => normal mode
2. DSP SRIO Mode : 1 Port 1x 5G
refclk : 156.25Mhz
serdes config function : csl_wiz8_sb_refclk156p25MHz_20bit_5Gbps.c
3. FPGA SRIO mode : 1x 5G
refclk : 125MHz(156.25MHz not support)
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SRIO Issues
1. FPGA, DSP Normal Mode
fpga port initialize/link initialize OK
but DSP port ok bit toggle : SPn_ERR_STAT Register(0x0290B158)
register value : 00020302 <-> 00020301
2. DSP side Serdes FEP Loopback mode enable, FPGA Side Normal Mode
always Port OK : SPn_ERR_STAT Register : 0x00000002
serdes LANExCTL_STS Register : 0xF0C0F0F3
PLL_CTL Register : 0xF0000F01
==> Using NWRITE : FPGA -> DSP(Src : FPGA Memory, Dst : DDR3 Memory(0x70000000 ~ 0x73ffffff)
==> work very well.
==> At this time, the SPn_ERR_STAT register value is changed to 0x00030002.
3. FPGA side Serdes FEP Loopback mode enable, DSP Side normal mode
always Port OK : SPn_ERR_STAT Register : 0x00000002
serdes LANExCTL_STS Register : 0xF0C0F0F2
PLL_CTL Register : 0xF0000F0F
==> Using NWRITE : DSP -> FPGA(Src Addr : internal memory, Dest Addr : DSP DDR3 Memory, length 65536)
using function : srioDirectIOWrSync(srcbuf, (UInt32 *)0x70000000, 65536, DEVICE_ID1_16BIT, 0, 0);
==> work very well.
==> At this time, the SPn_ERR_STAT register value is changed to 0x00000002.
** When the FEP Loopback on an FPGA or DSP works without any problems.
However, if both are in Normal Mode, SPn_ERR_STAT Register : 00020302 <-> 00020301(Port OK Toggle)
SRIO is not operating.
What is the problem?
please help me.....
thanks
