Other Parts Discussed in Thread: DM385
hi
we had met a problem when use DM385.
we use SW is IPNC_3_8 HW customer board.
in linux kernel I had enable PCI Bus.
I find that CPU is always wait after config PCI PLL。
code is in file arch/arm/mach-omap2/devices.c
function is named ti814x_pcie_pllcfg()
waiting place is in
while (!(omap_ctrl_readl(TI814X_CONTROL_PCIE_PLLSTATUS) & 0x1)){
cpu_relax();
}
all function as follow：
static inline void ti814x_pcie_pllcfg(void) {
if (cpu_is_ti814x()) {
/* TODO: Add bitfield macros for following */
omap_ctrl_writel(0x00000002, TI814X_SERDES_REFCLK_CTL);
omap_ctrl_writel(0x00000000, TI814X_CONTROL_PCIE_PLLCFG0);
omap_ctrl_writel(0x00640000, TI814X_CONTROL_PCIE_PLLCFG1);
omap_ctrl_writel(0x00000000, TI814X_CONTROL_PCIE_PLLCFG2);
omap_ctrl_writel(0x004008E0, TI814X_CONTROL_PCIE_PLLCFG3);
omap_ctrl_writel(0x0000609C, TI814X_CONTROL_PCIE_PLLCFG4);
/* Configure SERDES misc bits - values as is from h/w */
if (!cpu_is_dm385()) {
/* * TODO: MISCCFG write is not needed for PG2.x devices, * to be tested with if{} part removed */
if (omap_rev() > TI8148_REV_ES1_0)
omap_ctrl_writel(0x0000039E, TI814X_CONTROL_PCIE_MISCCFG);
else
omap_ctrl_writel(0x00000E7B, TI814X_CONTROL_SMA0);
}
udelay(50); omap_ctrl_writel(0x00000004, TI814X_CONTROL_PCIE_PLLCFG0);
udelay(50); omap_ctrl_writel(0x00000014, TI814X_CONTROL_PCIE_PLLCFG0);
udelay(50); omap_ctrl_writel(0x00000016, TI814X_CONTROL_PCIE_PLLCFG0);
udelay(50); omap_ctrl_writel(0x30000016, TI814X_CONTROL_PCIE_PLLCFG0);
udelay(50); omap_ctrl_writel(0x70007016, TI814X_CONTROL_PCIE_PLLCFG0);
udelay(200); omap_ctrl_writel(0x70007017, TI814X_CONTROL_PCIE_PLLCFG0);
while (!(omap_ctrl_readl(TI814X_CONTROL_PCIE_PLLSTATUS) & 0x1)){
cpu_relax();
}
}
so somebody can help me
what is problem with DM385 to use PCI?
Thank you very much!
