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C6678 EMIF16 NOR Flash: Change Async 1 Config Register while executing from same device

Alberto Chessa
Mastermind 6670 points

Hi,

When booting from EMIF16 CS0 NOR flash (C6678), so fetching code directly from flash, it is possible to change the A1CS register so too speed up the execution?

  • 0
    TI__Guru* 81335 points
    Hi Alberto,
    From my understanding, it is not possible. You may need to use two stage bootloader to increase the execution speed of NOR.

    Let me check with expert on this. Thank you for your patience.
  • 0 in reply to Raja
    Mastermind 6670 points
    My current boot loader is 2 stage. The second stage is small but I'm just evaluating the possibility to speed up its load time.

    For instance, my idea is to be sure there is not activity on the EMIF16 bus by using mfence and align my critical instructions (the one that change the A1CR and maybe the page register also) to an execution packet (128bytes) or to a cache line.
  • 0 in reply to Alberto Chessa
    TI__Mastermind 42545 points

    Hi Alberto,

    Your idea is a good one but you might want to take it a step further. I suggest that you create your two stage bootloader but expand on your first stage. The EMIF16 bootloader doesn't set up the PLLs so your SOC is still running at the bypass frequency. In addition, the maximum delays are set for the EMIF16 interface and these delays are based internal clock for the EMIF16 IP. This frequency is the SYSCLK1 frequency divided by 6 where SYSCLK1 is still equal to the bypass frequency of the system PLL. As you've determined, this will result in a very slow boot. I suggest that you load your first stage into internal memory and use it to set up the PLL, initialize the DDR3, reconfigure the EMIF16 registers for faster accesses and then copy the remaining boot code to the DDR3 memory. Once the boot code is loaded into DDR3, you can then jump to an entry point in the DDR3 and execute from there. 

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Mastermind 6670 points
    Hi,


    My first stage already behave as you suggest, that is it loads in internal memory, set the PLL, the EMIF16 and so on prior to load the application. I can try to program the PLL prior to copy into L2RAM, but I see on our custom board (with C6678 silicon 2.0) that the RBL already set the PLL to go at 1GHz.

    Also, sprugy5c, §2.2.1 say:

    The RBL configures the system PLL to set the device speed
    [...]
    The main PLL stays in bypass mode for no-boot, SPI, and I2C boot. For other boot modes, a PLL initialization sequence executes inside the boot ROM to configure the main PLL in PLL mode


    By the way, about the TI RBL: 3 boards boot at 1GHz, while one board at 800Mhz (same CPU version, same DEVSPEED, same external boot PGIO configuration).