We are interfacing the GPCM, CS2 to a FPGA using a 16-bit bus, multiplexing address and data. Writes to the fpga registers work correctly, but reads do not. The high byte of the data read looks correct, but the low byte is not. We've disabled all other devices on the GPMC bus.
What's really interesting is that the ChipScope capture seems to indicate that the data value read back is present on the bus some time after the transaction has ended (CPMC_CLK has stopped, CSn, EOn deasserted). We can also see that the FPGA presents valid data in response to asserting OEn.
Here are the config register values:
[ 63.149291] FpgaMem_get_cs2_info: GPMC_CS_CONFIG1_2=0x280c1211
[ 63.155395] FpgaMem_get_cs2_info: GPMC_CS_CONFIG2_2=0x141407
[ 63.161346] FpgaMem_get_cs2_info: GPMC_CS_CONFIG3_2=0xb0b06
[ 63.167144] FpgaMem_get_cs2_info: GPMC_CS_CONFIG4_2=0x1208120c
[ 63.173278] FpgaMem_get_cs2_info: GPMC_CS_CONFIG5_2=0x111616
[ 63.179199] FpgaMem_get_cs2_info: GPMC_CS_CONFIG6_2=0x100b0ac3
[ 63.185302] FpgaMem_get_cs2_info: GPMC_CS_CONFIG7_2=0x0f42
Note that we are running GPMC_CLK at GPMC_FCLK/2 - all signals are "half-speed".
Here is the ChipScope plot. We should be reading 0xFFFF, but we read 0xFF7e instead.
Can you see any reason why we are reading the wrong value?
