• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 535 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[OMAP-L137] IPR does not set in EDMA3 LLD when setting a second TCC

Gaston Schelotto
Expert 2850 points
Other Parts Discussed in Thread: OMAP-L137

I set a QDMA channel using LLD, then I wait for qtcc transfer completion by means of EDMA3_DRV_waitAndClearTcc function( hEdma, qtcc). This function waits forever because IPR bit does not set to 1. Previously I set a DMA transfer with a different tcc and it works fine.This is a piece of code inside a while(1) loop:

        // Wait for the Completion ISR.
        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_waitAndClearTcc (hEdma, tcc);

        // QDMA transfer configuration
        edma3_buffer.src = (Int32 *)(_large_bufferSrc);
        edma3_buffer.dst = (Int32 *)(_large_bufferDst);
        if (result == EDMA3_DRV_SOK)
            result = edma3_qtransfer_cfg(hEdma, &qtcc, edma3_buffer);

        // Wait for the Completion ISR.
        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_waitAndClearTcc (hEdma, qtcc);

 

What could be wrong? tcc=17, qtcc=22 and all EDMA3 functions return OK.

Platform used: OMAP-L137 with pspdrivers_01_30_00_06 and lld_01_11_00_03 EDMA3 version

  • 0
    TI__Expert 3990 points

    Are you setting the trigger word properly? You can use EDMA3_DRV_setQdmaTrigWord() for this. Please note that the trigger word should be written in the end after you set all other fields of the corresponding PaRAM Set.

    Please refer to edma3_lld_01_11_00_03\examples\edma3_driver\src\qdma_test.c for a basic QDMA example.

     

  • 0 in reply to Anuj Aggarwal
    Expert 2850 points

    Anuj Aggarwal said:
    Are you setting the trigger word properly?

    I think so. I refered to edma3_lld_01_11_00_03\examples\edma3_driver\src\qdma_test.c for this and I find this is a bit confusing. I have taken a look to qdma_test.c but I finally decided to take guidelines in edma3_drv.h (line 272), btw slightly different between them. This is the configuration code in my application with acnt=10240, bcnt=ccnt=1, BRCnt=0, Sync=A type, srcbidx=srccidx=desbidx=descidx=10240

    Uint32  qCh1Id = EDMA3_DRV_QDMA_CHANNEL_ANY;

        // Request any DMA channel
        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_requestChannel (    hEdma, &qCh1Id, final_tcc,
                                                (EDMA3_RM_EventQueue)0,
                                                NULL, NULL);

        if (result == EDMA3_DRV_SOK)
            result =  EDMA3_DRV_setQdmaTrigWord (    hEdma,     qCh1Id,
                                                    EDMA3_RM_QDMA_TRIG_DST);

        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_setSrcParams (    hEdma, chn_Id, (Uint32)(srcBuffer),
                                                EDMA3_DRV_ADDR_MODE_INCR,
                                                   EDMA3_DRV_W32BIT);

        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_setTransferParams (    hEdma,     qCh1Id, acnt, bcnt, ccnt,
                                                    BRCnt, sync);

        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_setSrcIndex (    hEdma,     qCh1Id, srcbidx, srccidx);

        if (result == EDMA3_DRV_SOK)
            result =  EDMA3_DRV_setDestIndex (    hEdma,     qCh1Id, desbidx, descidx);

        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_setOptField (hEdma,     qCh1Id, EDMA3_DRV_OPT_FIELD_TCINTEN, 1);

        // Set Destination Transfer Mode as Increment Mode.
        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_setOptField (    hEdma,     qCh1Id, EDMA3_DRV_OPT_FIELD_DAM,
                                                EDMA3_DRV_ADDR_MODE_INCR);

        if (result == EDMA3_DRV_SOK)
            result = EDMA3_DRV_setPaRAMEntry (    hEdma, qCh1Id,
                                            EDMA3_DRV_PARAM_ENTRY_DST,
                                            (Uint32)(dstBuffer));


    As I explained before no IPR is set after prior configuration, therefore program execution remains in EDMA3_DRV_waitAndClearTcc function, in this case waiting for a IPRbit22=1

    Any suggestions?

  • 0 in reply to Gaston Schelotto
    TI__Guru* 84110 points

    Please go back to the qdma_test.c example and try running it. You should find it to be a valid working example from which you can build a working application.

    The pseudo code in edma3_drv.h (line 272) was written as helper code to be a brief introduction to some of the steps needed. The concepts are there, but it is not intended to be a direct path to a working example. qdma_test.c is intended to be a working example. The differences between the two cases explain why your code does not work.

    First build and execute the qdma_test.c example. Then to learn how it works, step through the code while watching the PARAM entries for your QDMA channel. You will see which registers are set by each of the function calls and you may find which ones were not set correctly in your current code.

  • 0 in reply to RandyP
    Expert 2850 points

    Please forgive me , I didn't set TCINT=1 as I should.  Now IPRbit=22 is set. Thank you for your help.