Hello everybody,
I just read all the other posts on the topic but I didn't find the answer to my question so here we go:
For the project I am following in my company, I am required to feed a high frequency parallel DAC (2.304 MHz) through the EMIF interface. I know it is not exactly meant to supply data with a deterministic timing, but my team was doing it in previous projects with Analog Devices DSPs and it worked.
My situation is that I have a certain output buffer, placed in a dedicated DARAM memory block (and section) where the CPU writes, and the DMA (triggered by a timer) reads continuously the samples to "write" through the EMIF to the output DAC.
NOTE that no other accesses are issued by anything to this dedicated DARAM block.
When I preload the buffer and just read it with the DMA the transmission to the EMIF works just fine and the timing is perfect, so I have the same exact time between any two consecutive "writes"
However, if I also write with the CPU, not even to the buffer, but anywhere in the dedicated DARAM block (block 7), I can see that the DMA transfers to the EMIF are more or less randomly delayed of 0-1 clock cycles. This gives me a jitter on the output data that we can't accept.
My question is, how come that just writing something in the same block of DARAM can disturb the DMA read accesses? shouldn't the DARAM memory, per definition, allow two simultaneous accesses?
Thanks for your help,
V.
