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C6670 PCIe Root Complex Outbound Translation

Michael Slade
Prodigy 30 points

Hello all,

We have a C6670 design with the PCIe connected to a single endpoint (no switches). The C6670 is configured as a root complex, running Gen2, 2 lanes enabled. The link trains (LTSSM_STATE = 0x11) and the remote config registers are visible (can see Device ID). 64-bit mode is needed by the endpoint.

Problem: cannot seem to do outbound read transaction, to see the endpoint's control registers.

What I've looked at:
"PCI Express® Base Specification Revision 2.0" - If there is a specific section, what should be read?
"SPRABK8 PCIe Use Cases for KeyStone Devices"
"SPRUGS6C Peripheral Component Interconnect Express (PCIe) User Guide"

What I'd like:
Pseudo code to set up outbound translation.

Thanks!

  • 0
    TI__Guru* 81335 points

    Hi Michael,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please refer all the below my signature.

    Please go through below wiki for PCIe related FAQs and Resources and get back to us If the below resources does not help to solve the issue.

    http://processors.wiki.ti.com/index.php/PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

    Thank you.

  • 0
    TI__Mastermind 28085 points

    Hi Michael,

    I have tested MCSDK PCIe example between two C6670 EVMs, It is working fine. Better to use MCSDK PCIe example for your testing, you need to implement the EP part code on your EP device.

    In the MCSDK PCIe sample example, two DSP EVMs are used to test the PCIe driver. DSP 1 is configured as a Root Complex and DSP 2 is configured as End Point. Once the PCIe link is established, the following sequence of actions will happen:

    1. DSP 1 sends data to DSP 2 - DSP 2 waits to receive all the data

    2. DSP 2 sends the data back to DSP 1

    3. DSP 1 waits to receive all the data

    4. DSP 1 verifies if the received data matches the sent data and declares test pass or fail.

    Thanks,