Small delay written for the KeyStone bootloader User Guide.

Ats-nsmr

hello

I want to know the small delay written for the following document.
Please tell me the concrete numerical value.
KeyStone Architecture DSP Bootloader User Guide
3.7.2.4 Loading Image Into a Slave Device
[A small delay is required between the blocks.]
www.ti.com/.../sprugy5c.pdf

Best Regards
Ats-nsmr

over 10 years ago

0 Raja over 10 years ago

TI__Guru* 81335 points

Hi,
Who is your I2C master, Is it another DSP 66xx or FPGA?
Thank you.

0 Ats-nsmr over 10 years ago in reply to Raja

Intellectual 270 points

Hi Rajasekaran

Thank you for your reply.

I2C master is host processor(micro computer).

Best Regards
Ats-nsmr

0 Rahul Prabhu over 10 years ago in reply to Ats-nsmr

TI__Guru** 116170 points

Ats-nsmr,

I don`t think we have measured the smallest possible delay required as this may vary based on the setup but in the bootROM tests we were using 512 CPU cycle delay which seemed to work fine.

Regards,
Rahul

Processors

Processors forum

Small delay written for the KeyStone bootloader User Guide.