OMAP3530 GPMC Clock Synchronous to SYS_CLKOUT2

Jeff Pao said:

A customer is trying to connect his GPMC to an FPGA in synchronous mode for higher throughput.  He needs the GPMC_CLK signal even when not in a transaction on the GPMC bus.  GPMC_CLK seems to go away when not in a transaction.  Can he use SYS_CLKOUT2?  It seems to be off of the CORE_DPLL but not sure if there will be a fixed constant delay.

I certainly understand the issue your customer is facing in terms of needing an always running clock.  While they could certainly use sys_clkout2 for this purpose, if I were designing the FPGA, I would not feel comfortable depending on any timing relationship of the GPMC signals to this clock.  The datasheet timing is only specified relative to gpmc_clk.  Your customer will need to create some clock domain crossing logic in the FPGA to handle the interface.

Thanks Brandon.

Here's a translation of what I got from the OMAP3 product team (Vaibhav/Jeff Culverhouse).  

I would be little concerned about getting SYS_CLKOUT2 to drive GPMC_CLK, as there is a phase delay & frequency jitter that need to be taken into account.  If the FPGA can be architected differently to not be dependent on GPMC_CLK and SYS_CLKOUT2, please do so.

Jeff