VPBE Slave mode on DM6446

Hi,

Could you please explain what you mean by "I have observed strange behavior like a loss of the serration in lines 263, 264, 265."? Do you mean no color burst?

No, color burst is not the problem.  Check the scope image below.  The green trace is from another camera that I am syncing to.  The purple trace is the output from the Da Vinci, and the yellow line is the Vsync signal I am feeding to Da Vinci.  Notice in the analog output that the serration is not right.  I do not know what controls this.

Hi,

Our designer suggested that you verify that "VSTART is 3 HSYNC cycles after the external vsync is sampled."

Hello Jon,

I am thinking about developing a very similar genlock application and would like to know if you have success solving this problems. Do you have used a external VPBe CLK too or only the VCLK and HCLK? I didn`t find the FIELD pin too, only a LCD_FIELD. Is this one the FIELD described in the datasheet?

Thank you.

Hi,

You are correct, in the VPBE user guide, FIELD = LCD_FIELD.

Actually I never fully resolved this problem.  I found that the Field polarity could be inferred by the phase between VSYNC and HSYNC.  I did also supply a VPBE CLK.  As for the serration pulses, I still need to get back to debugging the problem.

Thank you Paul and Jon,

Paul, I have a digital image sensor connected in the VPFE and I am sending this to NTSC Composite video in the VENC of VPBE.   What  I want now is to "genlock" this composite output to another analog camera to avoid switching problems between this signals.  I have studied many GENLOCK PLL ICs to generate the clock to the VPBE and a video sync separator like the LM1881 to extract the syncs of the "reference" video.   However some os this ic`s are very hard to find nowadays because the technology is obsolete.

Now my main idea is to use a TVP5150AM1 (that I have already used in other projects) to receive the reference video signal and extract video syncs and generate the reference clock too, because I think this IC is line locked (the PLL locks to the reference horizontal line).   I will not use the data lines, only the syncs.

Do you think that this solution will work? In the TVP5150 there is some information about genlocking the color burst using an "output digital word" to syncronize. Do you think that this is relevant to my application? There is some way to use this "word" with the encoder of the DM6437 VPBE?

Yes, the TVP5150AM1 generates a line-locked output clock.

No, I don't think the Genlock feature is relevant to your application.

Regards,

Jim

We are using the 5150 for this type of purpose.  We are not using the digitized video data, just the sync signals.  I have so far found that you cannot use the signals from the TVP to directly drive the VPBE and generate a genlocked video signal.  I had to put in some logic to adjust the phasing a little.

Thnk you Jim and Jon,

Based in your scope signal, the phase adjustment is in the vertical sync pulse to make it happens 3 horizontal syncs before the vertical sync output of the 5150. It is it?  Maybe a counter that starts counting with the 5150 vertical sync and so counts the horizontal syncs until 3 Hsync before the next 5150 Vsync.

Is there any other phase problems with the horizontal sync or even with the SCLK?