questions about DDR2 works with OMAP-L138

Were all the DDR layout guidelines followed from the datasheet? You can email me your board design files and I can take a look at it for you to verify this.

If they were followed, it is most likely a timing configuration issue that can be solved by tweaking the DDR timing parameters in the controller.

Jeff

Zhang,

Did you recalculate all of the DDR2/mDDR peripheral timing values from your DDR2 datasheet?  Are you using the same PLL clock configurations as the EVM GEL?

-Tommy

Dear jeff:

I think I followed the datasheet , but i am not sure, this is the first time that i use ddr2, and also this is the first time to design 8 layer PCB. so many unsure factors.  I send a email to you ,  attachment is the design file. thanks.

B.r.

zhang

Dear Tommy:

I think i recalculated all of the DDR2/mDDR peripheral timing values , I am not sure, May you give me your email and i can email to you my C files? please help me to check whether it is right or not. I write the gel file according  to the omapl137evm.gel, only little changed. I can email it to you .

Thank you.

B.r.

zhang

Zhang Jingpo said:

I write the gel file according  to the omapl137evm.gel, only little changed.

Can you confirm that this was a typo and you used the L138 EVM GEL?  What does the DDR2 look like in the CCS memory view beyond 75MHz? 

-Tommy

Dear Tommy:

I am sure that I use the  omapl137evm.gel with changed,  not the L138 EVM GEL.

In CCS memory view, once I "Refresh" the DDR2 memory, some of them changed random, "Refresh" again maybe some others changed. You know that they will unchanged when the DDR2 work well. and I also use the memory fill to test , I use data 0x55555555 and 0xaaaaaaaa, some address can be filled with the data, not all.

BR,

zhang

There are issues with your layout which are in violation of our datasheet routing rules.

Stackup
Top: None
2: None
3: DDR Routing
4: Partial power plane
5: None
6: DDR Routing
7: DDR Routing
8: DDR Routing

You have to have an unbroken ground plane under the entire keepout region adjacent to *each* DDR routing layer. The viewer only shows partial ground planes under the L138 and the DDR on layers 2 and 4.  This is a likely cause of your failures at higher speeds, since there is no return path for the current.

Additionally please verify all the signals were skew matched according to the numbers in the datasheet. I cant check this with the free viewer.

Jeff

Zhang,

Can you compare your intialization sequence versus the L138 EVM gel?  I'm worried that there may be differences between the SDRAM EMIF on L137 and the DDR2 EMIF on L138.

-Tommy

Dear Jeff:

My design is 8-layer, so I should replan the DDR routing,  if I do like the following, is it ok ?

Top: DDR Routing
2: GND
3: DDR Routing
4: Partial power plane
5: GND
6: DDR Routing
7: GND
8: DDR Routing

if not , could you give me some suggestion ?

Also I will check the signals.

zhang

Dear Tommy :

I will rewrite the GEL file according to the L138 EVM GEL file.

Thanks

zhang