Strange hyperlynx simulation results at VLYNQ between TMS320C6424 and Spartan 6 FPGA

Kristian Skov

Other Parts Discussed in Thread: TMS320C6424

I get some strange results when I simulate the DSP (TMS320C6424) as TX and the FPGA (xilinx spartan 6) as RX.

I have downloaded the latest Ibis models so this should be allright.

A 47 Ohm series termination is used to reduce overshoot.

As seen below there is something unharmonic, because Risetime is 0.62ns and fall time is 2.5ns @100mHz causing my low period to be rather short.

Can someone please explain me what is going on?

Thanks in advance

over 15 years ago

0 Mukul Bhatnagar over 15 years ago

TI__Guru* 84075 points

Hi Kristian

Sorry for the delay in response. This post got off the radar somehow and didn't get addressed in due time.
I believe there was an issue with the ibis model. We have fixed it and will be pushing it to the web after some more verification. To expedite this for you, we have forwarded the updated ibis model to the TI local team supporting you. Hopefully you will get the updated file through them.

Let us know if you run into any issues.
Regards

Mukul