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DDR3 single ended trace impedance

Madhura IA
Prodigy 70 points

Hi,

As per the DDR3 routing guidelines for 66AK2E02, the single ended trace impedance should be 50ohm.

But usually for other processors like DaVinci, the single ended impedance for DDR3 trace should be between 50-75ohms with +/-5 tolerance.

Similarly do we have a range between which the single ended trace impedance should be chosen for K2E processor?What is the tolerance allowed?

Can we use 55ohm with +/-5 ohm tolerance?

Thanks and Regards,

Madhura

 

  • 0
    TI__Guru* 81335 points

    Hi Madhura,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please refer links below my signature.

    Please mention the document number of DDR routing guideline referred.

    Thank you.

  • 0 in reply to Raja
    Prodigy 70 points
    Hi Rajasekaran

    I am referring to document SPRABI1B Table 11, 12, 13.

    Thanks,
    Madhura
  • 0 in reply to Madhura IA
    TI__Guru* 81335 points

    Hi Madhura,
    But the description above those tables has the tolerance values documented that is +/-5%. The value should be between 47.5-52.5 Ohm.

     
    Thank you.

  • 0 in reply to Raja
    Prodigy 70 points
    Hi Rajasekaran,

    Please check the below details i have taken from DM816x datasheet,

    Single -ended impedance, Zo Min- 50 ohms Max- 75 ohms
    Impedance control Min- Z-5 Typ-Z Max-Z+5

    Z is the nominal singled-ended impedance selected for the PCB specified by Zo

    As per this impedance control or tolerance is +/-5 ohms and single ended impedance selected for the PCB is 50 -75 ohms.

    In the same way can we take pcb single ended impedance to be 55ohms controlled to +/-5% ?

    Hope you understood my question. I am referring to single ended impedance that can be chosen, not the impedance control.

    Thanks and Regards,
    Madhura
  • 0 in reply to Madhura IA
    TI__Mastermind 43660 points

    Hello Madhura,

    When you are going to design with Keystone2 device, you have to adhere to the design guidelines provided for Keystone2 device. The Davinci processors are from different family and you need not refer their guidelines for KS2 device.

    As mentioned in the DDR3 design requirement document, you have to follow the 50 ohm single ended impedance with +/-5% tolerance for proper functionality and no other impedance is allowed.

    The entire routing recommendations provided in SPRABI1B are framed based on 50 ohm single ended impedance only. When you change the impedance, you have to simulate the whole DDR3 interface for its functionality and its all up to your own risk.

    Hope you understand.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 70 points
    Hi Senthil,

    Thanks for clarifying.

    Regards,
    Madhura