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C6657 DDR3 PLL

Kzk
Genius 5785 points
Other Parts Discussed in Thread: TMS320C6657

Hello,

I don't use DDR3 in the system. I'd like to know what to do about DDR3 PLL to reduce power consumption. Does the DDR3 PLL come up in the bypass mode by default on powering up the device? I seem DDR3 PLL is not in the bypass mode after reset, because I see BYPASS = 0 (Bypass disabled.) and PLLRST = 0 (PLL reset is released.) in DDR3PLLCTL0 and DDR3PLLCTL1. Should I leave DDR3 PLL registers as reset default? Or should I re-set them to the bypass mode? Please give me advices.

Regards,
Kazu

  • 0
    TI__Guru* 81335 points
    Hi Kazu,
    Yes. Your understanding is correct.

    Please refer seciton "7.6 DD3 PLL" in data manual(SPRS814). The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, the DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.

    From my understaning, you shall leave that to default or set in bypass=1.
    Regarding power consumption, please refer the power estimation spreadsheet available in TMS320C6657 product page. In the Models section.
    Thank you.
  • 0 in reply to Raja
    Genius 5785 points

    Hello Rajasekaran,

    Thank you for your reply. I assumed the PLL comes up in the bypass mode by default because I saw the former description below. Thanks to you I understood.

    KeyStone PLL User Guide (SPRUGV2F) / 2.4 Bypass Mode
    CAUTION—The PLL comes up in Bypass mode by default on powering up the device. Once the PLL is initialized in PLL mode, it should not be re-initialized back to Bypass mode unless the user intends to power down the device.

    I'm also anxious about the latter description above. Is the description corresponding to Main PLL? (not DDR PLL)

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Mastermind 43660 points

    Hello Kazu,

    The statement that you captured is applicable for Main PLL and not for DDR PLL. The DDR PLL bypass is disabled by default and you need to enable it when you intend for power saving. However please note that the LPSC for DDR3 EMIF module is always on and you cannot disable it.

    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Genius 5785 points

    Hello Senthil,

    Could you tell me how to set to the bypass mode safely? I think there is not a descritpion about the initialization sequence of the bypass mode in PLL-UG (SPRUGV2F).

    Regards,
    Kazu

  • 0 in reply to Kzk
    TI__Mastermind 43660 points
    Hello Kazu,

    In PLL user guide section 3.5 DDR3 PLL Initialization Sequence, the second step is to put the DDR3 PLL in bypass mode. In your case, you can simply skip the further steps after putting the PLL in bypass.

    Regards,
    Senthil