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Question about AM1808 USB

g.f.
Guru 15520 points
Other Parts Discussed in Thread: AM1808

Hi,

I have a question about AM1808 USB.

Our AM1808 silicon revision is rev2.1 and using USB0.

There are errata "Advisory 2.1.10 USB0 PLL Mean Frequency Can Drift Across Large Temperature Swings".

I have a question about the following workaround of this Advisory:

/////////////////////////////////////////////////////////////////////

One such approach is to look for an absence of USB0 Core interrupts over a specified time window.

This window should be optimized for the expected USB traffic based upon the application.

/////////////////////////////////////////////////////////////////////

How to check USB communication abnormality,

if communication from the host isn't periodically and don't know when host communication will occur?

best regards,

g.f.

  • 0
    TI__Guru**** 393215 points

    Moving this to the AM1X forum.

  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 84475 points
    Hi
    If the USB communication is not periodic or deterministic, and the product is being exposed to temp variations in the ranges listed in the errata, it might be best to do a periodic reset of the USB PHY PLL to re calibrate (as listed in the para below the one you quoted).

    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Guru 15520 points
    Hi Mukul,

    Thank you for the reply and sorry for the delay.

    I understood, but I don't want to reset USB PHY PLL periodically because
    the reset might happen during normal USB communication.

    Is there any method to detect unstable USB PHY PLL so that I don't need to reset periodically?
    I'm thinking of checking the CFGCHIP2(Chip Configuration 2) register bit17 "USB0PHYCLKGD" periodically.
    Does USB0PHYCLKGD change from 1 to 0 if USB PHY PLL gets unstable?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Mastermind 43660 points

    Hello G.F,

    Whatever the method to detect unstable USB PHY PLL, the USB PHY reset is still required to re-calibrate the PLL at the reset temperature.

    A PHY reset also implies re-enumeration of all devices. There is no way to re-calibrate the USB0 PHY without a re-enumeration.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Guru 15520 points
    Hi Senthill,

    Thank you for the reply.

    I understood that USB PHY reset is required.
    In errata sheet Advisory 2.1.10, it seem that PLL will lose lock.
    I want to reset the USB PHY when PLL became unstable as following:

    1.Check CFGCHIP2.USB0PHYCLKGD periodically
    2.If CFGCHIP2.USB0PHYCLKGD = 0, reset USB PHY
    If CFGCHIP2.USB0PHYCLKGD = 1, do nothing

    So, does CFGCHIP2.USB0PHYCLKGD be 0(PLL unlock) if Advisory 2.1.10 occurred?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Mastermind 43660 points
    Hello G.F,

    I am not very sure about the status of USB0PHYCLKGD when there is a PLL drift. I will check with the SoC team and get back to you.

    Thanks for your patience.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Guru 15520 points
    Hi Senthil,

    Thank you so much.
    Okay, I will wait.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 84475 points
    Hi G.F
    No , from our testing, USBPHYCLKGD bit polling is not a reliable method to check for PLL drift over temp. While the PLL might eventually loose lock, you will start seeing communication break before PLL looses lock and additionally this bit might or might not be set after PLL looses lock.
    This bit is primarily used as part of initialization, but we cannot recommend using this for checking against PLL drift on the decision making on when to reset the USB PHY etc.
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Guru 15520 points
    Hi Mukul,

    Thank you so much for the support.

    Okay, I understood that USBPHYCLKGD should not be used for checking PLL unlock state.
    So, I guess there are no method to check the communication break from the AM1808 status registers.
    The only thing that user can do is just reset the USB PLL periodically
    whether communication breaked or not. Is it correct?

    best regards,
    g.f.
  • 0 in reply to Mukul Bhatnagar
    Guru 15520 points
    Hi Mukul,

    Thank you so much for the support.

    Okay, I understood that USBPHYCLKGD should not be used for checking PLL unlock state.
    So, I guess there are no method to check the communication break from the AM1808 status registers.
    The only thing that user can do is just reset the PLL periodically
    whether communication breaked or not.
    Is it correct?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 84475 points
    Hi G.F
    Yes.

    >>if communication from the host isn't periodically and don't know when host communication will occur?
    Since the USB communication in your customer's application is not deterministic, and cannot be instrumented to look for core interrupts over a period of time etc, if the application is being subjected to temperature variations that can cause the issue , then reseting USB periodically might be the only way.
    In some end applications, customers have on board temperature sensing, if something like this is available on the customer board and can communicate to AM18x, that could be another way , on "when" to do a USB PHY reset.

    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Guru 15520 points
    Hi Mukul,

    Thank you so much and I'm sorry for taking your time.
    I understood.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru* 84475 points
    No problem.
    I hope if your customer is making newer boards , they can move to the latest revision of the silicon, where this issue is fixed.
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Guru 15520 points
    Thank you.
    Yes, I will suggest to the customer.

    best regards,
    g.f.