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C6657 MCBSP event triggers edma

giorgos tsoumplekas
Expert 1840 points

Dear all,

We use the C6657  DSP core.

An  EDMA interrupt must be triggered,  when either a transfer or a receive event comes to MCBSP peripheral.

Regarding the Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. A) document, the EDMA synchronization events for the MCSBP  are the following events 36,37,38 for the RX0/TX0 and RX1 /TX1 corresponding.

Should we set  both of the  requested logical channel (LCh) and  the channel  on which the completion/error interrupt(Tcc) is generated as a EDMA3_DRV_HW_CHANNEL_EVENT_xx ?

Can we use any other channel id for the Tcc and LCh?

Best regards,

George

  • 0
    TI__Guru* 81335 points
    Hi George,
    Moving this thread over device forum for faster response.
    Thank you for your patience.
  • 0
    TI__Mastermind 35645 points

    Hi George,

    Thanks for your post.

    In my opinion, it is enough to set only the channel on which the completion/error interrupt (Tcc) is generated and actually logical channel (LCh) is bound to which EDMA PaRAM set OPT field is required. Thiere are EDMA driver API which can be used to read/set various optional parameters for an EDMA3 transfer, like enable/disable completion interrupts, enable/disable chaining, setting the transfer mode (A/AB Sync), setting the FIFO width etc.

    While requesting for a specific DMA channel, there is a specific SoC file "soc.h" maintained which contains the mapping of any hardware events to the respective peripherals. There are #defines for McBSP Tx and McBSP Rx channels which are mapped to EDMA driver hardware channel events 2 & 3 as  below:

    #define EDMA3_DRV_HW_CHANNEL_MCBSP_TX        EDMA3_DRV_HW_CHANNEL_EVENT_2

    #define EDMA3_DRV_HW_CHANNEL_MCBSP_RX        EDMA3_DRV_HW_CHANNEL_EVENT_3

    The above #defines are used by the MCBSP driver and the same event EDMA3_DRV_HW_CHANNEL_EVENT_2/3 could be mapped to some other peripheral also, but that needs to modified in the SoC specific file.

    Kindly refer the edma3_drv.h header file in the EDMA3_LLD_DRV package for the respective DMA channel assignments to EDMA events and check the enum "EDMA3_DRV_HW_CHANNEL_EVENT" in the  same header file.

    For more information, please refer the Keystone McBSP user guide as below:

    http://www.ti.com/lit/ug/spruhh0/spruhh0.pdf

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Expert 1840 points
    Hello,
    Thank you for the prompt reply.

    I have already checked the example under pdk6657_1_2 (Digital Loopback using the mcbsp driver) and both of the TCC and Logical channel are bound in the corresponding channel for the MCBSP event that we are waiting . If we do not use this idea, what is the crrect value that the logical channel should have should have, when we call the EDMA3_DRV_requestChannel
    Thank you
    George
  • 0 in reply to giorgos tsoumplekas
    TI__Mastermind 35645 points

    Hi,

    Thanks for your update.

    User can request any specific logical channel through its channel id "pLCh" along with EDMA allocated resources (PaRAM sets, TCC) for a particular DMA/QDMA/LINK. In case of DMA/QDMA channel, the allocated channel no would be the value of the logical channel and in case of LINK channel, the allocated PaRAM Set number would be returned as the logical channel number. User can also request for a specific TCC which needs to be allocated with DMA/QDMA channel.

    For any DMA/QDMA channels, after allocating all the EDMA3 resources, this API sets the TCC field of the OPT PaRAM Word with the allocated TCC. It also sets the event queue for the channel allocated.

    Thanks & regards,

    Sivaraj K

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