TMS320C6655 IBIS MODEL DDR3 Controller termination value

Hello Adam,

Welocme to TI E2E Forum!

DDR3 includes on die termination (ODT) for the data bus interface. The termination in the DDR memory is used for write accesses. The termination in the C665x is used for reads. Currently the documentation for the DDR3 controller states that the ODT for reads should always be full Thevenin termination.

The impedance is determined by the value of the resistor you have connected to you PTV pin. If you have the recommended 45.3 ohm resistor you will have a full Thevenin termination with 45ohms to VTT.

The full Thevenin is selected by default by placing a 0x1 in the RD_LOCKAL_ODT field in the DDR_PHY_CNTL_1 registers. You can find this in Table 4-25 of the DDR3 Memory Controller Users Guide.

Regards,
Senthil

Hi Senthil,

How is this modeled in the C6655 IBIS model?

Please show me the portion of code that indicates an internal Thevenin termination is being applied in simulation for a read access.

thanks,

Adam

Hi Adam,

This is clearly defined in line No: 61 and used in the model selector section line No: 840 in the IBIS model tms320C6657_55_r1p2.ibis.

Note: By default this model comes up with the recommend value 45 ohms for full thevenin, if you change the value in the board, you may see some variations with respect to measured and simulated waveform.

Regards

Antony

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Thanks Antony,

I'm inexperienced with modeling and DDR3 for that matter but this indicates to me that they are TX values. For the case where the DDR3 Controller on the DSP is writing to the DDR3 memory I would define as TX.

For RX it should be the DDR3 memory driving the DQ and DQS lines and do the DQ and DQS get terminated at the DSP by the controller? If so is this where in the model the termination values are set?


************************************************************************************
| DDR ACC
|************************************************************************************
[Model Selector] ACC_OUT
| bshtltcscdvg.ibs [6 Sep 2011 Revision 1.6]
|
CSCDVG_SLOWEST_9MA TX 45 ohms Slowest (SR1 1; SR0 1)
|
CSCDVG_SLOW_9MA TX 45 ohms Slow (SR1 1; SR0 0)
|
CSCDVG_FAST_9MA TX 45 ohms Fast (SR1 0; SR0 1)
|
CSCDVG_FASTEST_9MA TX 45 ohms Fastest (SR1 0; SR0 0)


The DDR3
| Definitions:
| Drive strength defined by resistor value connected to PTV15 pin
| 9MA_FT9MA : Full Termination Thevenin [45 ohm] [45ohm to Vtt]



Thanks,

Adam