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Delay in CPU access to L2.

Sandeep Rao30
Prodigy 565 points

I would like to  understand the penalty in running code (and data) out of L2  with L1 cache DISABLED.

So CPU will be directly accessing L2 for both program and data. I ran some tests using the LCDK6748.

Case A:  Code and Program in L2, with L1 configured as full cache.

Case B: Code and Program again in L2 with L1 caching disabled.

I found that case B is about 8 times slower than Case A. Is this expected?

  • 0
    TI__Expert 4760 points

    Hello Sandeep,

    Higher level memeory (L1) is closer to CPU ,CPU always request from the highest level memory if the address is not present in L1, cache H/W gets it from lower level (L2) or External memory

    L1 memory provides zero wait state access, say for example L2 -> L1 (1-8 cycles)

    In your experiment if you disable the L1 cache, absolutely it may take more cycle to execute the instructions  or slower because the CPU executes from the lower level memory (L2) in the compared with the highest level (L1).

    Regards

    Antony

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