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C6657 EDMA Dst FIFO register set

Genius 5785 points

Hello,

I consider a certain transfer for EDMA. A destination address of 1st transfer becomes a source address of 2nd transfer. I seem that EDMA TC will change an order between read commands for the subsequent TR and the write commands for the previous TR. Please let me know if I can forbid this functionality. For realizing the transfer safely, should I start 2nd transfer after completion of 1st transfer? Or can I use a chain-triggered transfer? Please refer below.

Keystone EDMA3 User Guide (SPRUGS5A)
2.1.3 EDMA3 Transfer Controller (EDMA3TC) (P.29)

Regards,
Kazu

  • Hi Kazu,

    Thanks for your post.

    I think, we cannot forbid the order between read commands and write commands.  The TC write controller can start issuing write commands only when sufficient data is been read in the data FIFO for the write controller to issue write commands following the rules for command fragmentation and optimization. It seems there are specific rules for command fragmentation and for more details, please refer section 2.12.1.2 from the EDMA controller user guide as below:

    http://www.ti.com/lit/ug/sprugs5a/sprugs5a.pdf

    Thanks & regards,

    Sivaraj K

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  • Hello Sivaraj,

    Thank you for your reply. I'm sorry, but my question was not clear. My concern is not the command fragmentation but the TR pipelining and data ordering. I think this exchange between a read command for a subsequent TR and a write command for a previous TR is not occurred if I send one TR from CC to TC at a time. So I mentioned 1st/2nd transfer sequence and chain-triggerd transfer before. Is my understanding correct?

    Regards,
    Kazu

  • Hi Kazu,

    Yes, your understanding is correct. The data ordering should be, first a read command for a subsequent TR followed by a write command for a previous TR.

    Thanks & regards,

    Sivaraj K

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