Question about C6670 IPC interrupt

g.f.

Guru 15520 points

Hi,

I have a questions about C6670 IPC interrupt.

I'm generating IPC interrupt by writing '1' to IPCGRx(IPC Generation Register) bit0.

The interrupt is generated from Core0 to Core1 and from Core2 to Core3.

The IPC interrupt is assigned to Interrupt Event#90.

So, when IPC was generated from Core0 and Core2 at the same time, is an exclusive access control needed?

best regards,

g.f.

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

For my understanding, IPC not generate the interrupt from multiple cores at the same time, once complete the core0 interrupt and then generate the core2 interrupt based on your test applicant.

Thanks,

0 g.f. over 10 years ago in reply to Ganapathi Dhandapani95

Guru 15520 points

Hi Ganapathi,

Thank you for the reply.
Is there a priority ? Is Core 0 have the highest priority against IPC and Core4 the lowest?

best regards,
g.f.

0 Ganapathi Dhandapani95 over 10 years ago in reply to g.f.

TI__Mastermind 28085 points

Hi,

I have discussed with my team, IPC is generate the interrupt from multiple cores at the same time. C6670 device have four IPC registers, it can interrupt other cores at a same time.

In IPC interrupt receive operation corepac receive multiple IPC interrupt, it will processed one by one based on IPC interrupt priority. Example: core0 receive IPC interrupt from core2 and core3 means, it processed core2 interrupt and then process the core3 interrupt.

Thanks,

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Question about C6670 IPC interrupt