C6678 PCIe address configuration by boot CPU

Eddie3909

C6678 PCI boot mode

Is there a way to configure CCS to output a header file that can be used by the host CPU to configure PCI bar registers? For example, the host CPU would need to know where the non-cached L2, MSM, DDR is so it can configure its bars for loading the DSP after boot.

Cheers2u

Eddie

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

Refer TI provided pcie demo code, it should be help you for configure PCIe BAR for L2, MSM, DDR.
MCSDK Path: "\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c"

In PCIe Boot mode, IBL is configured the PCIe BAR configuration registers. If you want to change the PCIe BAR configuration size mean, you can modified the IBL source and update the rebuild IBL binary to your setup.

Function: iblPCIeWorkaround()
Path: “\ti\mcsdk_x_xx_xx_xx\tools\boot_loader\ibl\src\device\c66x\c66xinit.c”

Please go through below wiki for more information.
processors.wiki.ti.com/.../PCI_Express_(PCIe)_Resource_Wiki_for_Keystone_Devices

Thanks,

0 Eddie3909 over 10 years ago in reply to Ganapathi Dhandapani95

Guru 10385 points

Hi Ganapathi

Sorry for not being more specific in my question. Let me try again. We are looking for a CCS generated include file that lists DSP internal memory addresses for our Host CPU to program its PCI bars. Its not for programming the C6678 PCIe. Its for the host CPU to include in its files for compilation.

Cheers
Eddie

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

Is there a way to configure CCS to output a header file that can be used by the host CPU to configure PCI bar registers?

We do not have this type of examples, you can develop your self.

Thanks,

Processors

Processors forum

C6678 PCIe address configuration by boot CPU