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C6670 SRIO boot configuration

henlee
Intellectual 840 points


On our C6670 board, the system clock is 153.6 MHz and the SRIO clock is 312.5 MHz.

SRIO BOOTMODE bits are described in sprs689d:

bits 3-9:  Table 2-5 "Serial Rapid I/O Configuration Field Descriptions"

bits 10-12:  Table 2-13 "C66x CorePac System PLL Configuration"

Questions:

1. Does the system clock configuration in bits 10-12 have anything to do with the SRIO configuration in bits 3-9?

2. Since our system clock is 153.6MHz which is not in Table 2-13, should we configure bits 10-12 for the closest frequency in the table (156.25 MHz)?

3. Are there any other registers which need to be set differently to factor in the expected 153.6/156.25 reduction in DSP frequency?

  • 0
    TI__Mastermind 28085 points
    Hi,

    Ans1: No. Refer section "2.4 Boot Modes Supported and PLL Settings" on data manual.

    Ans2 and Ans3: I will check with our hardware team and try to answer your questions. Please take a look at section "2.2 Device Initialization" of the KeyStone Architecture DSP Bootloader User's Guide.
    www.ti.com.cn/.../sprugy5c.pdf

    Thanks,
  • 0
    TI__Mastermind 43660 points
    Hello Henlee,

    1. The system clock configuration does not have any effect on the SRIO configuration. You have to configure both the fields in boot mode register.
    2. We recommend you to keep the system clock as one of the value listed in table 2.13. However, you can use 153.6MHz and set the configuration bits to next higher value (in your case 156.25MHz).
    3. To my knowledge, there is no register to set the factor in reduction.

    Regards,
    Senthil